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Tsun Hsiao Huang

4 years experience in Analog integrated circuit design with Phase-Locked Loop and analog circuit.

Work experience

May 2011Present

Analog Integrated Circuit Design Engineer

IC plus corporation

<1>  In  90nm process. To design PLLs with calibration Kvco.  The PLL  opearte between 300MHz~375MHz and 400MHz~475MHz for DDR clock and CPU clock, respectively.
<2> In 0.18um process. To design 125MHz and 135MHz PLL for CPU clock. In this project also maintain POR, LDO, Crystal Oscillator, Band-gap, and IO circuit. I expect that this product can be mass production.


Sep 2008Nov 2010


National taipei university of technology (Institute of Computer and Communication Engineering)
  • Implemented a fast-digital calibration technique for charge pump in phase-locked loop operating at 2.4G~2.6GHz.
  • Utilized PROTEL to complete the PCB layout and used Spectre and Hspice to complete chip design.
  • Studied measurement of high-frequency technology courses in National Nano Device Laboratories (NDL).
  • The design team was honoredin 10th Macronix Golden Silicon Awards semiconductor design competition
  • Joined IC design competition in Chip Implementation Center (CIC).
  • Submitted a paper in IET Electronics Letters.
Sep 2008Jun 2010


Vanung university (Computer Science and Information Engineering)
  • Analysed DC and AC circuit in electronics and circuitry courses.
  • Utilized VERILOG to design hardware and studied the relationship between instruction and hardware in the high-end hardware design courses.
  • Studied digital logic design and practice.