Analog Integrated Circuit Design Engineer
<1> In 90nm process. To design PLLs with calibration Kvco. The PLL opearte between 300MHz~375MHz and 400MHz~475MHz for DDR clock and CPU clock, respectively.
<2> In 0.18um process. To design 125MHz and 135MHz PLL for CPU clock. In this project also maintain POR, LDO, Crystal Oscillator, Band-gap, and IO circuit. I expect that this product can be mass production.