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Oct 2008Present


Université de Bretagne Occidentale

The possibility to create, synthesize and manipulate molecules and objects at nano scale that behave like electronic devices gives new opportunities for the development of information technologies. A number of nanoscale circuit architectures has already been proposed, each one presenting its own advantages and challenges. But for these fabrics to become usable for real life circuits, the community needs the right set of abstractions along with a set of tools (CAD tools) for application design automation on these emerging fabrics. The design of these CAD tools poses a new set of challenges not encountered with conventional CMOS technology. These challenges come basically from the intrinsic characteristics of the nanodevices used (like high defect rates), and from the way they are assembled together.

My research focuses on the design and the development of a generic and evolutive set of CAD tools capable to quickly adapt to these technological challenges while providing a common set of abstractions, regardless of the target technology used. Based on the experience with Madeo framework and its extensions for nanoscale reconfigurable architectures, I am proposing a new framework for application design automation and circuit design targeting crossbar-based hybrid nano/CMOS architectures.

Work experience

May 2008Sep 2008

Research Engineer

Université de Bretagne Occidentale

ValMadeo Project - design and synthesis of a data-flow turbo decoder. 

  • Design a methodology for hierarchical composition and generation of circuits from combinatorial blocks produced by MadeoLite;
  • Design and implementation of a multi-level testing methodology for synthesis results validation;
  • Automatic pipeline generation from combinatorial logic block produced by MadeoLite;
  • EDIF generation for the Celoxica FPGA development kit.
Apr 2007Jun 2008

Research Assistant

Université de Bretagne Occidentale

NanoCAD: Design Automation Methods for Emerging Nanoscale Technologies

  • Design of a generic and evolutive framework for physical circuit synthesis on a wide variety of nanoarchitectures. Design of  suited models and implementation of specific algorithms (flooplan, placement, routing)

System Modeling and Routing Architecture Synthesis

  • Design and development of a framework for parallel application development and synthesis on System on Chip (SoC) hardware architectures;
  • Design and implementation of a behavioral description language, named SyNe, for state machine description and parallel composition;
  • SyNe language integration with the Avel composition language into the tool flow of MORPHEUS project;
  • Integration of ADeVa specification language into the tool flow of MORPHEUS project via an ADeVa control-data-flow graph (CDFG) mapping
  • Design of a framework for network synthesis with applications to network algorithms validation
May 2005Nov 2005


Ovidius University of Constanta

Avizier WEB --

  • Design and development of an web-based multicast communication system. 

SmartCard Solutions - The Smart Choice

Smartcard-based integrated service accessing.

  • Participation to Microsoft Imagine Cup, 2005;
  • Design of a software architecture for Web service composition and exploitation based on smart-cards


Romanian - native language

English - fluent

French - fluent

Turkish - beginner



Kyokushinkay karate, Shinto Club Constanta, 8 kyu;Aquatic sports: kayak (sea kayak), surf, and swimming;Oriental philosophy, especially zen bouddhisme;

Technical Knowledge

Operating Systems: MacOS X, Linux, Windows, Solaris, FreeBSD, MS-DOS. 

Programming Languages: Smalltalk, Java, C/C++, C#, Occam, Handel-C, VHDL, Pascal, x86 Assembler, SQL, 

T-SQL, PLPSQL, OO Pascal (Delphi). 

Web Programming: Html, XHtml, CSS, Java-Script, Seaside, Asp.Net. 

Database: PostgreSQL, Microsoft Access, Microsoft SQL Server. 

Others: Madeo, Microsoft Visual Studio .Net, JSP, Flash, SDL, ADO.NET, XML Web Services. 


Computer software engineer, with experience in object-oriented software design and implementation, high-level automatic harware synthesis, compilation techniques, distributed systems, combinatorial optimization algorithms. Interested in automatic circuit design using novel technologies (like nanoelectronics, quantum dots, etc.).

Words that define me

novelty seeking, curious, adventurous, flexible, spontaneous, open-minded, energetic, creative  

decisive, focused, analitical, logical, original, exact

persuasive, adaptable, competitive, problem-solver, independent


  • C. Teodorov, "Comparing Crossbar-based nano/CMOS Architectures", Design & Technology of Integrated Systems (DTIS'10), 2010, Hammamet, Tunisia.
  • C. Dezan, C. Teodorov, L. Lagadec, M. Leuchtenburg, T. Wang, P. Narayanan, A. Moritz, “Toward a Frameword for Designing Applications onto Hybrid Nano/CMOS Fabrics”, Microelectronics Journal, vol. 40, issues 4-5, p. 656-664, april-may 2009.
  • C.Teodorov, D.Picard, and B.Pottier, “From Sensor Networks to Concurrent Systems”, Internal report, june 2008.
  • D. Picard, B.Pottier, and C. Teodorov. “Process System Modeling for RSoC”, 4th International Workshop on Reconfigurable Communication Centric System-on-Chip, 9-11 july 2008, Barcelona, Spain.
  • C. Teodorov, C. Dezan, L. Lagadec, “Automatic Circuit Layout for Emerging Nanoscale Architectures”, GDR SOC-SIP, 2008, Paris, France.
  • C.Teodorov, “NaBoo : A Generic, Evolutive CAD Framework for Automatic Circuit Layout on Emerging Nanoscale Architectures“, Université de Bretagne Occidentale, 3 june 2008, Brest, France.
  • C. Teodorov, “NanoCAD: Design Automation Methods for Emerging Nanoscale Technologies. A Survey of Nanoscale Computing Architectures and Associated CAD Tools”, Commented Bibliography, Université de Bretagne Occidentale, january 2008, Brest, France.
  • D. Picard, B. Pottier, C. Teodorov, “Process Networks on Reconfigurable SoC”, Aether-Morpheus Workshop - Autumn School 2007 From reconfigurable to self-adaptative computing (AMWAS’07), 8-11 octomber 2007, Paris, France.
  • C. Teodorov, J. Knablein, B. Pottier, “Quick integration of high level tools in MORPHEUS: The case of SpecEdit”, Aether-Morpheus Workshop - Autumn School 2007 From reconfigurable to self-adaptative computing (AMWAS’07), 8-11 octomber 2007, Paris, France.
  • C. Teodorov, H. Dutta, B. Pottier, “An Abstract Approach for System Description and Synthesis”, First Workshop on Constraint Programming for Hardware Design, 20 september 2007, Rennes, France.
  • C. Teodorov, B. Pottier, “SpecEdit Modelling and CDFG translation“, Technical Report, Université de Bretagne Occidentale, 28 august 2007, Brest, France.
  • C. Amariei, C. Teodorov, E. Fabiani, B. Pottier, “Modeling sensor networks as concurrent systems“, Fourth International Conference on Networked Sensing Systems (INSS’07), 6 - 8 june 2007, Braunschweig, Germany.
  • C. Amariei, C. Teodorov, “Investigating sensor networks with concurrent sequencial processes and Smalltalk“, Fourth International Conference on Networked Sensing Systems (INSS’07), 6 - 8 juin 2007, Braunschweig, Germany.
  • Ciprian Teodorov, “Modelling sensor networks as concurrent systems“, Technical Report, Université de Bretagne Occidentale, 11 june 2007, Brest, France. 


Web Programming
Reconfigurale Architectures
Nanoscale Computing Architectures
Combinatorial Optimisation Algorithms
Distributed Systems
Compilation Techniques
Automated hardware synthesis
Object Oriented Design