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Electronic Engineer M.Sc. graduate (First-Class Honors degree) with more than 1 year experience in the digital design flow, from architectural modeling to implementation and verification.

Heartily enthusiast about digital electronics and state-of-the-art semiconductor technology, with proficiency in designing integrated electronic circuits and digital hardware architectures for both FPGA and ASIC flows and great capabilities on low-power optimizations and high-performance techniques.

Passionate about IT and technology, motivated and committed hard-worker, open-minded and adaptable to new situations, always looking for challenges and opportunities to expand his knowledge.

Work History


Junior FPGA Digital Design Engineer

SIAE Microelettronica

Core activities:
 - Complete digital design flow for DSP applications in the TLC field within FPGA context: from architectural description and Matlab modeling and validation, through VHDL design and verification using Modelsim,  to final target implementation including STA and using constraints to meet design requirements.
 - Maintenance and enhancement of already existing modules
 - Hardware prototypes bring-up and on-chip system debug.
 - Development of control software and user interface in Embedded-C (FW) and TCL
 - Cooperating with and providing support to other teams to fulfill targets.


Web designer

DML Auto Service s.r.l.

Website designing and developing with Serif WebPlus x5.


Grape farmer

Azienda agricola Zanella F.lli

Fixed-term summer work for grape harvesting.


Web programmer intern

Daneswood Solutions, Exeter (UK)

Website  developed with proprietary CMS and Adobe suite; Javascript and PHP programming.



M.Sc. in Electronic Engineering - First Class Honors (108/110) 

Polytechnique of Turin

Solid background on digital electronics with knowledge in design, synthesis and implementation of integrated circuits, characterized by low power and/or high speed analysis and optimizations.
Good knowledge of digital information processing elements architectures (CPUs, GPUs, DSPs, ASIPs), along with good insights on IC design flow and related EDA tools (Synopsys Design Compiler, Cadence Virtuoso and SoC Encounter).

Relevant courses: Integrated Digital Systems, Low Power Electronic Systems, Integrated Systems Architecture, Integrated Systems Technology,Digital Microelectronics.


Responsible of vinification filtering machinery

Collis Veneto Wine Group

Fixed-term summer work for grape harvesting and vinification.


B.Sc. in IT Engineering - Second Class Honours, Division I (99/110)

University of Padua

Information Technology formation with strong Maths and Physics attitude on fields like Electronics, Automation, Telecommunications.

Relevant courses: Signal Analysis, Telecommunications,  Circuit Theory, Electronics.


Computer Science High School

I.T.I.S. "V.E. Marzotto"

C, C# programming, together with UML, HTML, PHP, SQL and humanities.

Courses - Polytechnique of Turin

Integrated Digital Systems/30L

Integrated Systems Technology/30L Low Power Electronics Systems/30L
Integrated Systems Architecture/30L Digital Microelectronics/23 Analog and TLC  Electronics/26
Operating Systems/30 Bioinformatics/30 Sensors and Measurement Systems/23
High Speed Electron Devices/30 Guiding Electromagnetic Systems/27 Finite Element Modeling/25


Italian:    Native

English:  IELTS Cambridge Certification - 7.5/9 - Level  C1 of CEFR

Skills + Competences


  • Very good: VHDL (plus some Verilog) and Modelsim
  • Very good: FPGA design flow (Xilinx Vivado and Altera Quartus)
  • Good: ASIC design flow (Synopsys Design Compiler, Cadence Virtuoso and SoC Encounter), System-C
  • Very good: Eagle, LTSpice
  • Good: Analogue electronics, RF circuits, PCB layout and manufacturing
  • Very good: Manual Diagnostic Instrumentation (Oscilloscope, Spectrum Analyser, Multimeter, Signal Generator) 


  • Very good: C, Embedded C, TCL
  • Very good: Matlab, LaTeX
  • Good: C++,  OpenCL, OpenCV library, assembly, Bash shell scripting, Python, Git
  • Good: C#, Java, PHP, HTML, SQL, UML (Visual Paradigm)
  • Very good knowledge of UNIX-like (Linux Mint and Ubuntu in particular) and Windows systems
  • Very good: Office and OpenOffice suites (Word, Excel, PowerPoint, Access, Visio and open-source alternatives)


  • Flexible and reliable, committed hard-worker with Excellent communication skills (both oral and written)
  • Very quick-learner, always willing to get involved with new challenges
  • Optimistic and curious, intuitive and self-motivated problem solver
  • Very good team player or individual, good leader when needed
  • Concrete criticism and analytical thinking: always trying to see the big picture


Academic Projects

  • Design of a Heterogeneous System-on-Chip for Computer Vision applications (M.Sc. thesis project)

A SoC with a soft-core Rocket Chip CPU together with a spatial filtering hardware accelerator was designed to efficiently run the Canny Edge Detector algorithm. The components were connected through a common AXI bus, and the system has been developed on a Xilinx Zynq-7000 SoC through the Vivado IDE, achieving speed-up factors of more than 4x.

  • Micro-programmed Digital Signal Processor designed for arithmetic operations with complex numbers

Design and implementation of a processing unit for efficient execution of the "butterfly" operation, basic building block for the Fast-Fourier Transform in the Cooley-Tuckey algorithm. The unit is designed for multiplications and additions/subtractions between complex numbers providing the smallest error and no rounding bias (fixed point representation with rounding to the nearest even scheme, 1/2 LSB maximum error). By analyzing the algorithm steps and mapping them down to the hardware architecture datapath optimizations are deduced and the number of operators, variables (registers) and global busses has been reduced: this lead to the optimal trade off between performance and needed resources. The micro-programmed control unit generates instruction addresses and the content of the corresponding memory locations contain the correct datapath signals, as well as potential conditional jumps (based on status signals). The architecture has been validated with VHDL and C testbenches.

  • Optimization of WCRA Filter for protein alignment on a systolic array hardware accelerator

Optimization of the systolic array WCRA filter (Word-Count Reduced Alphabet) developed in conjunction with the DGS (Dynamic Gap Selector) variant of the Smith-Waterman algorithm. Post-synthesis analysis followed, both for FPGA and ASIC design flows.
Tools used: Mentor Modelsim, Synopsys DC, SoC Encounter, Quartus (area and power post-synthesis analysis).

  • Comparison of different implementations of a FIR digital filter

A lowpass FIR  filter was designed with Matlab, C and VHDL; results from different models were collected and compared to validate the custom filter. Digital implementation was optimized with pipeline technique to achieve higher frequency and throughput. Power and area occupation comparisons done at  synthesized and implemented levels.
Tools used: Mentor Modelsim, Synopsys Design Compiler, SoC Encounter (area and power post-synthesis analysis).

  • TTA ASIP optimized for DCT-based applications

Realization of a Transport-Triggered Architecture Application Specific Instruction-set Processor with open-source TCE tool environment, to efficiently execute Discrete Cosine Transform applications, thanks to the addition of custom operations to the base ISA.
Tools used: Mentor Modelsim, Synopsys Design Compiler, SoC Encounter (area and power post-synthesis analysis).

  • Globally-Asynchronous Locally-Synchronous (GALS) system with custom SPI peripheral on FPGA and microcontroller board

Design and implementation on an Altera DE2 FPGA board of a custom SPI slave able to act as a SRAM memory controller, alongside with the master SPI microcontroller firmware.
Tools used: Altera Quartus, Mentor Modelsim.

  • Design and development of a microcontroller-based datalogger module (B.Sc. thesis project)

An Arduino-compatible "plug-in" module was created with the aim of acquiring and storing environmental values (temperature and humidity) for a fuel cell safety device. Scope of the project was the development of the embedded C firmware controlling the whole system. An USB interface provided the capability of downloading the samples (stored in a dedicated SPI EEPROM) to a common PC through UART interface. The module PCB (completely created by myself with UV LED exposure and etching) included an 16x2 LCD display and some buttons used for user interaction with the system.

  • Design and implementation of a 4-state ACS unit in HLS for CC decoding

Design of a 4-state Add-Compare-Select unit in SystemC High-Level Synthesis language and a complete testbench; translate the code to Verilog and follow the ASIC flow. 
Tools used: Mentor Modelsim, Synopsys Design Compiler, SoC Encounter.

  • Hardware acceleration of a protein local alignment algorithm on GPU with OpenCL

Parallelize the execution of a protein local alignment algorithm (Smith-Waterman) leveraging the GPGPU computing high concurrency provided by OpenCL environment, by dividing the main problem into smaller computational tasks, executed by many processing elements.

  • Matlab Ion/Ioff model validation of a Trapezoidal Triple-Gate FinFET

Implementation of a Ion/Ioff model for a Trapezoidal Triple-Gate FinFET in Matlab and validation.