- Design of a Heterogeneous System-on-Chip for Computer Vision applications (M.Sc. thesis project)
A SoC with a soft-core Rocket Chip CPU together with a spatial filtering hardware accelerator was designed to efficiently run the Canny Edge Detector algorithm. The components were connected through a common AXI bus, and the system has been developed on a Xilinx Zynq-7000 SoC through the Vivado IDE, achieving speed-up factors of more than 4x.
- Micro-programmed Digital Signal Processor designed for arithmetic operations with complex numbers
Design and implementation of a processing unit for efficient execution of the "butterfly" operation, basic building block for the Fast-Fourier Transform in the Cooley-Tuckey algorithm. The unit is designed for multiplications and additions/subtractions between complex numbers providing the smallest error and no rounding bias (fixed point representation with rounding to the nearest even scheme, 1/2 LSB maximum error). By analyzing the algorithm steps and mapping them down to the hardware architecture datapath optimizations are deduced and the number of operators, variables (registers) and global busses has been reduced: this lead to the optimal trade off between performance and needed resources. The micro-programmed control unit generates instruction addresses and the content of the corresponding memory locations contain the correct datapath signals, as well as potential conditional jumps (based on status signals). The architecture has been validated with VHDL and C testbenches.
- Optimization of WCRA Filter for protein alignment on a systolic array hardware accelerator
Optimization of the systolic array WCRA filter (Word-Count Reduced Alphabet) developed in conjunction with the DGS (Dynamic Gap Selector) variant of the Smith-Waterman algorithm. Post-synthesis analysis followed, both for FPGA and ASIC design flows. Tools used: Mentor Modelsim, Synopsys Design Compiler, SoC Encounter, Altera Quartus.
- TTA ASIP optimized for DCT-based applications
Realization of a Transport-Triggered Architecture Application Specific Instruction-set Processor with open-source TCE tool environment, to efficiently execute Discrete Cosine Transform applications, thanks to the addition of custom operations to the base ISA. Tools used: Mentor Modelsim, Synopsys Design Compiler, SoC Encounter.
- GALS system with custom SPI peripheral on FPGA and microcontroller board
Design and implementation on an Altera DE2 FPGA board of a custom SPI slave able to act as a SRAM memory controller, alongside with the master SPI microcontroller firmware. Tools used: Altera Quartus, Mentor Modelsim.
- Design and development of a microcontroller-based datalogger module (B.Sc. thesis project)
An Arduino-compatible "plug-in" module was created with the aim of acquiring and storing environmental values (temperature and humidity) for a fuel cell safety device. Scope of the project was the development of the embedded C firmware controlling the whole system. An USB interface provided the capability of downloading the samples (stored in a dedicated SPI EEPROM) to a common PC through UART interface. The module PCB (completely created by myself with UV LED exposure and etching) included an 16x2 LCD display and some buttons used for user interaction with the system.
- Design and implementation of a 4-state ACS unit in HLS for CC decoding
Design of a 4-state Add-Compare-Select unit in SystemC High-Level Synthesis language and a complete testbench; translate the code to Verilog and follow the ASIC flow. Tools used: Mentor Modelsim, Synopsys Design Compiler, SoC Encounter.
- Hardware acceleration of a protein local alignment algorithm on GPU with OpenCL
Parallelize the execution of a protein local alignment algorithm (Smith-Waterman) leveraging the GPGPU computing high concurrency provided by OpenCL environment, by dividing the main problem into smaller computational tasks, executed by many processing elements.
- Comparison of different implementations of a FIR digital fiter
A lowpass FIR filter was designed with Matlab, C and VHDL; results from different models were collected and compared to validate the custom filter. Digital implementation was optimized with pipeline technique to achieve higher frequency and throughput. Tools used: Mentor Modelsim, Synopsys Design Compiler, SoC Encounter.
- Matlab Ion/Ioff model validation of a Trapezoidal Triple-Gate FinFET
Implementation of a Ion/Ioff model for a Trapezoidal Triple-Gate FinFET in Matlab and validation.