Goal: To be a core VLSI Design,Test and Verification Engineer Professional Experience: Chip Design tools- Cadence, Virtuso layout Editor,DRC,LVS, NC-Verilog. HDLs: VHDL and Verilog HVLs: VHDL, Verification with 'e' Embedded programming. Simulation tools - Modelsim Altera, Quartus, Xilinx. Atalanta: ATPG for Combinational and Sequential Circuits and Tetramax. •Software : C, Perl
Implementation of an FPGA into an ASIC
Jul 2009 - Present
- RF Testing for the powercast kit.
- Debugging of low level code for future modules.
- pcb repairs.
Nov 2008 - May 2009
Hardware Engineer(CO OP)
Critical Link LLC
• Involved in the Design and Verification of custom design models of Host Bridge controller -Tsi107, SDRam, Spansion S29 series Flash Rom and Timer Configurations of an embedded system for an Altera CPLD using VHDL. • Perform Timing Simulation and Verifications of these models using Modelsim 6.3c tool. • Write Design Verification and Test procedure documents for the above Models
Jun 2008 - Aug 2008
RF Application Engineering Intern
• Customer service request resolution for RF Drivers Application on Qualcomm Modem IC. • Design verification for RF drivers of the MSM (Mobile station modem) using Trace 32 ICD and Agilent 8960 analyzer. • Developed a structural as well as application document of RF drivers for the customer as well as for internal team training and reference.
Aug 2005 - Jul 2007
atos origin india ltd.
• Analyzed, estimated, developed and tested (self and peer). • Prepared technical Design and performed code reviews (self and peer). • Performed product audits for project monthly to check and adhere to CMMi Level 5 standards.
Aug 2007 - May 2009
- Hardware Engineering, VLSI , ASIC design.
2002 - 2005
University of Mumbai
Implemented an Interpolated FIR Filter over an FIR filter using Matlab Filter Builder Tool BoX Converted the design into a VHDL code to be Implemented on a XILINX FPGA. Simulated the Design in ModelSim
Designed my own chip of microporcessor from Layout to GDS-II format. Wrote the Verilog code and converted to layout using NC-VERILOG Defined Bit SLiced Architecture for the Microprocessor. DRC vs LVS
VHDL Design for a CPLD implementation and Verification. Designing verification models in VHDL for Bridge controllers Taking workshop on VHDL for Undergradute School.