Focus System Administration and EDA local liason and Physical Design Engineer.
New design center infrastructure design including purchasing them locally/importing the needed high end servers to make planned configurations and application installations. PC based design environment implementation. File server management on filer systems and backup procedures planning with native scripting capability in addition to legato solistice and backbone vault application usages on unix based systems like sun blade servers and hp desktops. Linux based opteron servers management
User linux workstations and simulation servers O&S upgrade RH4.8 to RH5.5 smootly. Server Room Organization including planning, purchasing all required equipments and installations on the rack based on best practices. Internet circuit monitoring and performance metrics collection. Alternative backup service provider replacements. New servers quote collection with the best discounted prices after negotiations. Memory module failure problems fixes. Old equipment recycling. New PC tool installations
Nortel office pbx phone system management Gigabit switch management Project disk space usage monitoring and future disk space requirement planning Print services management CIFS configuration on user laptops.
TSMC 65nm IP development setup implementation: Cadence 6 project setup, depot creation, process flow selection, reference libraries contact, project and user simulation data transfers and their migration from cadence5 to cadence6, setup same envrionment in San Jose. New bonding stream file generation procedure enhancements like scribe layer addition. NCSim simulation servers runtime speed improvement researches. Tool licenses like matlab, istlcim001 icmanage cache implementation and upgrades. New tool installations like eclipse verilog editor, debussy, conformal, primitime, design analyzer. Vendor IP integration and verification implementations. PDK upgrades, reference library upgrade monitoring, new depot requests. expired licenses renewal: vcar, assura rcx, ncsim, assura drc,Aruba wireless access point quote collection, installation, configuration, new linux workstation initial configuration. new ups and battery replacement quote collection and configuration. user project disk space mounting.User laptop configurations. NIS master configuration on virtual servers.. Calibre submit host problem fixes. New EoD cluster accesses to Istanbul users. b.scr all systems monitoring capability script. GMSL family of products web page creation and updates. Tape library backup updates.
· Worked on product development of ·27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer·27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer·27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer·Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel (MAX9259/60) ·Fully Programmable Serializer/Deserializer with UART/I2C Control Channel MAX9257/58 · HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263/64 · HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface MAX9265 ·16-Bit GMSL Serializer with Coax or
STP Cable Drive MAX9271 · 28-Bit GMSL Deserializer for Coax or STP Cable MAX9272 · GMSL Coax/TP 3.125Gbps Serializer with Parallel/LVDS System Interface and De-Serializer with parallel CMOS outputs MAX9275/76/77/79/80/81 · GMSL Coax/TP 3.125Gbps Deserializer with MIPI CSI-2 Output Interface MAX9288/90 · GMSL Coax/TP 3.12Gbps Deserializer with LVDS System Interface MAX9278/82/85/87 · Gigabit Multimedia Serial Link Serializer with LVDS System Interface MAX9249 · HDCP Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9266 · Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 · 3.12 Gbps Serializer with HDMI Input and Coax/TP Output MAX9293 analogue chip I.C. layouts.
Senior Design Engineer Cypress Semiconductor, Consumer and Computation Division Istanbul Desig Center Apr 2002 – July 2005
FocusCAD Engineer/System Administrator/Network Engineer
· Local responsibility for providing technical support on corporate CAD tools (CADENCE/MENTOR) and flows and system administration related duties in which are including working both independently and collaboratively with other CAD support team members and corporate ITG departments to address specific problems, issues and bugs to manage the system with the minimum downtime. Solving service requests, monitoring / tracking bugs. This experience in configuring and developing CAD tools and process set up, work strong cooperation with the global cad a part of a team. Perl, Skill, Awk scripting capability is presented for routine final verification checks to manage them in a more efficient and productive manner to save time/money while working under pressure and to tight deadlines. Work with local solution providers/ISP/vendors to make the current ones more efficient, more reliable to make a more efficient design house environment. Design center office move is planned/scheduled and done with a minimal downtime.
Focus CAD & System Administrator
·Provided technical expert support on JCATS combat simulation model for staffs level army commands, weapon system parameters, war systems analysis, and other Electronic Intelligence systems. Maintained numerous simulation sessions about research & development of the sophisticated intelligence database systems. Articulate spokesman; hand-picked to develop and present briefings with the help of JANUS simulation tool to the Turkish Land Forces senior staff and officers on Turkish Janus Warfare Simulation System, Missile Defense, weapon systems, threat combat systems.
Focus Cell Development & Physical Design
·Successfully created ICs on CMOS processes in which UMC 0.25um or TSMC 0.18um which is including high performance speed/linearity, power, area tradeoffs and signal integrity avoidance on analog ICs like including layouts of analog cells, basic building blocks and high speed IO's like Low-Voltage-Differential-Signaling (LVDS) I/O pairs bias and driver cells operating at 622 MHz. in 0.25 micron CMOS technology, universal analog receiver and transmitter layouts. Simulated & analyzed extracted parasitic components with DRACULA about the voltage-drop and transmission line effects of the LVDS I/Os on the test chip according to the specified/suitable package type with ELDO of Mentor Graphics.
Istanbul Technical University (Turkey), Electrical and Telecom. Engineering Oct 1997- Courses Completed No Thesis/MSC Degr.: Digital Electronics Circuit, Design of Integrated Data Converters Active Network Synthesis Applied Advanced Functional Analysis Senstivity and Tolerance Analysis Information Theory Theory of a Complex Variable Functions Statistical Signal Processing
Contemporary Sciences Foundation Executive MBA Program Oct 1998-Jun 1999
(1 year program) Pre-MBA certificated by Maine Business School University of Maine and Marmara University Contemporary Sciences Foundation. Hazine ve Sermaye Piyasalari Muhasebe Borclar Hukuku Ticaret Hukuku Yönetim Muhasebesi Maliyet Muhasebesi Finansal Analiz Yönetim, İnsan & Kaynakları İşletme Politikası Is Hukuku Vergi Hukuku
Microelectronics, physically designed Tsividis a band-gap reference circuit that is including a vertical NPN device and MOS devices working at sub-threshold region operation as a undergraduate term work and successfully implemented this standard cell in 3μm CMOS. VLSI Lab. and VLSI lab. Thesis managed by Prof. Duran Leblebici. Undergraduate electronics program courses list.and telecommunications program courses list.