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Master Degree in Electrical and Electronic Engineering

Hadaf institute of Higher education, Sari, Iran

Design & Simulation Analog CMOS RF Frequency Dividers & Oscillators

Thesis : "Design and Simulation of Analog Frequency Divider by 2 and Improve Its Performance in terms of Locking Range"


Bachelor Degree in Electronics Engineering Technology

Hadaf institute of Higher education, Sari, Iran

Electronic Engineering Technology

Thesis : "DC motor control using HMT - HMR Transceiver"


Associate Degree in Electronics Engineering

Imam Sadiq(AS) Technical Institute of Babol, Iran

General Electronic Trends



Locking Range Enhancement of Divide by 2 Injection Locked Frequency Divider using Phase Shift technique - DOI: 10.1049/iet-cds.2016.0394

IET Circuits, Devices & Systems Journal

Received 03/10/2016, Accepted 23/01/2017, Revised 06/01/2017, Published 24/01/2017


2nd International Conference & 3rd National Conference on New Technologies Application in Engineering

Ferdowsi University of Mashhad, Iran

Improving the implementation of ADPLL using LC Voltage Controlled Oscillator


International conference on new research in science and engineering

Tehran University, Iran

A low-phase noise source injection-coupled LC quadrature oscillator with tail noise filter


7th Iranian Conference on Electrical and Electronic Engineering (ICEEE2015)

Islamic Azad University of gonabad - IEEE Iran Section

Improved Feed-forward using Derivative superposition in LNA (Low Noise Amplifier)

Article Registration No. : HN10108830687 - Supported by IEEE Iran Section 


Organic Solar Cells - Theory and Practice - Online Verified Course

Technical University of Denmark (DTU)

Verified Certificate at

English Proficiency ( IELTS test result )

Reading          6.5

Writing            6

Listening        6.5

Speaking       7 

Overall Band Score         6.5


Design and Implementation of Electronic Hardwares and Circuits

Cadence Virtuoso Custom IC Design & Layout - Agilent ADS - Microwind Layout Design- Protel 99SE - Altium Designer  -  MATLAB

BGA Chip Repair Machine

BGA rework station,Motherboard repair,laptop repair, Chip repair and rework 

Operating Systems

Microsoft Windows , Linux , Mac OS 

Network +

Active And Passive Computer Network infrastructure design and implementation

MS Office software

MS Word,MS Excel,MS Powerpoint,MS Project,MS Access

Web Design

CIW Web Design and ASP.Net Framework Based Apps

M.Sc Thesis Abstract

Proposed Structure of this dissertation presents technique of injection locking enhancement in divide by 2 injection locked frequency divider using phase shifter circuit. The ILFD’s structure is based on dual resonance 4th order LC tank CMOS cross coupled oscillator. Dual resonance resonator provides wide frequency range, however it has dual band locking range which lower band locking range regarding lower resonance frequency and higher band locking range regarding higher resonance frequency. Therefore, employed resistor in the tank contribute to overlap dual band and make a single band frequency range. With using phase shifter circuit, the ILFD exhibits wider locking range while the resistor is less than previous structure that needs higher resistor to reach an equal amount. The current generated by the phase shifter circuit with new angle toward oscillator current injects into resonator tank and produce a new locking range with new angle of locking. Differential outputs of the ILFD are connected to phase shifter’s input. When differential signals have peak value, no current flow through phase shifter circuit and when differential signals passing their transition time, an appropriate current with phase angle close to ideal phase shift angle will be produced. The effect of phase shifter current is analyzed in this work and simulation results evaluate the proposed idea. Simulations of this structure has been done using TSMC CMOS 0.18μm process with supply voltage of 0.95 V. The proposed ILFD has 7.7mA current and 7.32mW power consumption. The ILFD with phase shifter circuit provides locking range of 5.25 GHz (4.3 GHz – 9.55 GHz) and relative locking of 75.81% at incident power of 0 dBm.