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Charan Kocherlakota

Senior Design Engineer,Sankalp Semiconductor Pvt.Ltd


A candidate with a bachelor's degree in electronics and communication engineering and sound knowledge about working for Analog Mixed signal & RF Layouts, seeks a challenging role to execute Module Layouts to Chip Level.

Work Experience:

  • 4+ years of Analog Custom and RF Layout expertise in deep sub micron process till 28nm CMOS, SOI and BICMOS technologies.
  • Good knowledge and Implementation of  Analog Layout techniques such as Device matching , Noise Isolation, shielding, EM, IR and Latchup Prevention Techniques.
  • Expertise in understanding  circuits and Layout of RF Building Block such as VCO,LNA,Transmission Power Control, base band building blocks such as ADC, DAC, LPF, Reference Generators, Amplifiers and Power Management blocks such as LDO, POR, BGR, PWM etc.
  • Experience in Module level Floor planning, Power and Critical Analog signal Planning, Chip level Routing plan and congestion analysis, PAD connected signal routing.
  • Good Understanding of Deep sub micron issues such as LOD, WPE, PSE and OSE.
  • Experience in DRC, DFM, LVS, ERC, Antenna and post layout extraction.
  • Experience in handling Module Level Layouts which includes mentoring team members,tracking schedule and delivering Area efficient  quality layout.
  • Experience in delivering high Quality in a reduced cycle time using Cadence Virtuoso XL features such as Modgen, Cloning, Wire Assistant, Annotation Browser, Constraint Manager, VSR and VCAR.
  • Good verbal and written communication skills.
  • Good at logical thinking , Debugging and Troubleshooting.
  • Training freshers in areas of  Skill Scripting , Analog layout concepts & held  responsibility of directly mentoring three engineers.


  • Skill, Perl and Shell Scripting.
  • Cadence Virtuoso IC617 ,VXL Layout Tool.
  • Verification tools such as Calibre,Assura,Hercules and PVS.

Awards and Recognitions

  • "Customer champion" for the quarter April - June 2014 for delivering high quality layout using Vxl features reducing productive cycle time .
  • Customer Champion Oct-Dec 2014- "The new insight you provided was the greatest victory in the effort of SAWLESS LNA IN AADI".
  • Quality Champion Jan-March,2015 Excellent efforts in MB logic layout with the challenges of fixed area, aspect ratio & pin locations.

Work History

Jan 2014Present

RFIC Layout Engineer


Responsible for Layout and Verification of multiple blocks in High Speed RF Circuits (Rx & Tx Section).

Transmission Power Control Block:

  • This module seeks the RF input from antenna and varies the power of the signal based on the requirement .
  • Responsible for the complete floor planning , Power planning to Clamps and ESD diodes , RF input signal from PAD .
  • Responsible for mentoring team members  and tracking schedule to ensure quality layout of all sub blocks in a timely manner.

Sawless LNA and VCO:

  • Sawless LNA Module for GSM and VCO with a frequency range of 4.8 to 5GHz.
  • Challenging role of LNA input PAD Route plan,Transformer and Inductor Placement planning,maintaining Keep out area constraints.
  • NTN and DNW isolation techniques used to reduce Power loss for Passive Devices.
  • Shielding techniques used for Voltage control input in VCO,layout techniques to achieve high Q factor for LC load.


  • Responsible for the complete floor planning , placement & routing of pwm block and area estimation,floor planning of Buck switching regulator.
  • Challenges of meeting EM and NTN isolation techniques to avoid Ground Switching Noise.
Apr 2013Dec 2013

Analog Layout Engineer

Texas Instruments(Contractor)

Responsible for Layout & Verification of Various amplifiers,bias generators,filters in baseband section.

ADC-1Ghz LAN port:

  • Worked on Input amplifier in Low pass filter , clock tree synthesis in the clock driver , top level routing and verification of 8-bit flash ADC . Responsible for delivering the complete module on time and played  the role of acting lead.

Storage Product Chip:(BICMOS)

  • Worked on Chip Level Congestion Analysis and Physical Verification.
  • Chip level Antenna error solving was challenging and a great learning.
  • Meeting ESD Resistance for all the I/O PADS and Parasitic improvements on Critical Analog signals was challenging.
Jun 2012Present

AMS Layout Engineer

Sankalp semiconductors

physical design and verification of multiple Analog and Mixed Signal modules in 28nm , 40nm,65nm and 180nm.

Power Management Module:

  • Responsible for delivering the complete Module .
  • Worked on LDO , Bandgap reference , Resistor dividers , Test Mux , LDO output amplifier and buffer , Brown out detection module and Custom Logics.

10 Bit Current Steering DAC:

  • Worked on Current mirror array & bias blocks.
  • Worked closely with the designer on Parasitic extractions and improvements.



12th Grade

Visakha Junior College

Percentage : 93.7%