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Summary

Poised, fast-learning and articulate engineer with an interest in image and video processing for embedded systems that lead to 10+ years in novel research and development, patents, video quality studies and technical reports.

Known for excellent client-facing and collaboration skills, with strengths in Intellectual Property (IP) valuation and development of content for sales/marketing collateral, I have contributed in proposals and presentations that set up seven-figure contracts and mergers. 

Work History

Dec 2013Present

Chief Commercial Officer

THE RELATIONSHIP NINJAS

Developed brand and customer acquisition strategies for web site traffic growth.

Designed web site UI, expanded product offering and finalized commercial partnership agreements. 

Oct 2011Nov 2013

Member of Technical Staff, Staff (Staff Engineer)

Qualcomm

Main contact and liaison for presentation, technological transfers and technical support for IP clients, both internal and external (hardware, software and IC teams).

Instigated and prototyped development of new video IP roadmap and research for 2D-to-3D conversion, depth enhancement, blur reduction. 

Joined internal patent review board to identify and evaluate patentability of peers' inventions.

Sep 2009Oct 2011

Senior Video Engineer

IDT

Key contributor in the design, research, development, testing and support of real-time frame-rate conversion (FRC w/ Motion Estimation/Compensation) IP for System-on-Chip (SoC) in displays that lead to multiple design-wins.

Development of video quality test metrics and methodology that lead to diffusion of demo material for proposals, training for clients and competitive analysis. 

May 2006Sep 2009

DSP Video Architect

Silicon Optix

Built Montreal research branch office for Silicon Optix and managed 2 group integrations as the team was subsequently acquired by IDT, then Qualcomm.

Key contributor in the design, development, testing, technical writing and support of proprietary real-time video processing algorithms (IP), including 3D and MPEG noise reduction, de-interlacing, cadence detection, scaling.  These IP blocks served as the core for state-of-the-art Integrated Circuits (IC).

Dec 2003Mar 2006

Algorithm Designer & Sales Engineer 

Algolith

Key member in proposals and technical presentations that have landed seven-figure contracts to expand sales in the home-theater and video processing algorithm markets.

Assisted in the organization, setup and presentation of multiple industry-related trade-shows, including CES, SID, CEDIA, etc.

Video algorithm optimization, vectorization and bit-accurate modeling for hardware (FPGA) integration, resolving quantification and architectural problems.

Education

20032005

Masters in Electrical Engineering, Signal Processing

Université de Sherbrooke
19992003

Bachelors in Electrical Engineering, Telecommunications

Université de Montréal École Polytechnique