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Nilay Ghumre

Component Design Engineer

Work experience

2010Present

Component Design Engineer

INTEL MOBILE COMMUNICATION
Component Design Engineer Design the Verification Environment from scratch in System Verilog UVM. Worked on IP RTL Verification Task(System Verilog UVM and Specman) Worked on Test Chip Design Activity as well as RTL and GLS Verification activity with Pattern Generation and Resimulation. Achievement Two Recognition Awards from the LINZ, Austria team for the effort of ISP Verification Task Soft skills

Education

20082010

MASTERS

Visvesvaraya National Institute of Technology
20032006

B.Eng