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Nilakantha Singh Deo

Project Assistant ,Indian Institute of Science

Work experience

Oct 2014Present

Project Assistant

IISC Bangalore

project assistant

  • Modelling of uncertainty to analyse sustainability in the product life cycle assessment.
  • Funded by: Boeing
Jul 2014Oct 2014

Intern

VLSI GURU
  • Ethernet packet loopback design verification using SystemVerilog

 Description: Design checks the incoming Ethernet packets at the receive interface for CRC, SOF errors, data len errors, etc. Packet is looped back on Transmit interface if it is good, else dropped. As part of this design verification we developed testbenchs with generate all types of Ethernet packets and also developed reference model for the self checking the design behaviour.

  • Tools used: Questasim
  • Duration: 3 months
  • Responsibilities:
  • Listing down features, scenarios
  • Testplan development
  • Developing test bench architecture
  • Coding Testbench components including reference model and checkers
  • Verification closure using Functional coverage & code coverage as closing criteria.

 AXI VIP Development using SystemVerilog

  • Description: VIP component development for AXI3.0 protocol. As part of this project we have developed BFM, Generator, Monitor, Coverage models. We have also developed basic scenarios targeting all features of AXI protocol.
  • Tools used: Questasim
  • Duration: 6 months
  • Responsibilities:
  • Developing VIP architecture
  • Coding VIP components
  • Validating AXI VIP using AXI slave model.

 

Jun 2009Jun 2012

Lecturer

EAST Odisha
  • Teach fundamental and advanced subjects such as VLSI design, Microprocessors and microcontrollers, Sensors and signals in Electronics and Instrumentation Engineering as a Lecturer, in Dept. of Electronics and Instrumentation Engineering.
  • Teach using tools like Cadence, Mentor graphics, Tanner, MATLAB, Xilinx (VHDL/Verilog), Lab View
  • Has set up labs for EEM, PCI, IDS I and II, microprocessors and to demonstrate concepts using programming 8085 ,microcontrollers

Education

20122014

Master of Technology (M.Tech.)

Kalinga Institute of Industrial Technlogy
20042008

Bachelor of Technology (B.Tech.)

Silicon Institute of Technology

Skills

Perl
C++
C
Arduino
KiCAD
Tanner EDA
AVR Studio
Proteus
Embedded Systems
Xilinx System Generator
ARM KEIL
Xilinx ISE
LTSpice
Cadence Encounter
FPGA
Simulink
Matlab
Cadence Virtuoso
Questa Sim (Mentor Graphics)
VLSI functional verification
VLSI CAD

References

Proffessor                HOD Dept. of Electronics EAST Odisha Engineering College               Phone: 09861746037 

Prof. Srinibasa Padhy ([email protected]) Professor, School of Electronics,              KIIT University, Odisha.               Phone: 07381842044