Focused on quantum information filed, especially the quantum dot system.
Bachelor's Degree in Physics
Sep 2006Jun 2010
National Cheng Kung University, Taiwan
Book prize in freshman & sophomore year
United Microelectronics Corporation (UMC), Tainan, Taiwan
Advanced Tech. Development -- Process Integration Engineer
A+ in 2017 annual performance appraisal.
Develop advanced 22nm platform, coordinate 1st shuttle tape-out for process capability, device model, IP functionality build-up.
Designed rule TSK to verify development weak points, including WELL isolation, OPC capability, LDE(MBE, LOD, shadowing effect), and certain process weak spots.
Established 22nm mask boolean, designed FEoL dummy patterns for healthy process development.
Designed OPC recipe with OPC team for device boost and process robustness.
Coordinate 22nm 2nd shuttle tape-out for product yield verification.
A+ in 2014 & 2015 annual performance appraisals.
Develop advanced 28nm HKMG platform(HPC/HPC+), focus on layout dependence effect(LDE), Ion uniformity(IDU) improvement and model issues.
Improved Broadcom HPL yield from 33% to 75% by optimizing mask OPC.
Improved nFET long channel WIW U% from 16% to 6%.
Coordinate quarterly 28nm HKMG shuttle tape-out for customer's early IP/product verification, customer including Marvell, Faraday, MaxLinear and Renesas. Successfully drove MaxLinear's product for mass production in 2015 Q1.
Handled Broadcom 28nm HKMG MPW HPL tape-out, including customer's test chips and model testkey. Successfully transferred to fab for risk production in 2015 Q4.
Established solid tape-out working flow to achieve zero excursion.
Skilled in tape-out procedure, mask boolean, and OPC(optical proximity correction)
Excelled in 28nm/22nm HKMG design support manual, especially for Topological Layout Rule(TLR) and device family/truth table.
Identified product/IP weak pattern for WAT/Yield/Reliability trouble shooting by Calibre nmDRC and DFM under Linux OS.
Resolved WAT/Yield/Reliability problems by using Boolean to redesign mask patterns or optimizing OPC patterns.
28nm HKMG Process
Excelled in 28nm/22nm HKMG process flow.
Improved process healthy by analyzing circuit layout design and WAT/in-line data.
Languages：Fluent in Mandarin and English
Computer Skills：Python/ Linux OS / Shell Script / Klayout / Mentor DRC
Activities：Volunteer in remote areas
Interests：Mountain Climbing, Basketball, Reading, Personal Investment and Personal Fitness