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  • Saddle Brook nj


I have strong experience in logic design, simulation, and timing closure. I have previously worked in big teams of twenty logic designers down to small teams of three. I am currently working as a lone engineer handling a project from beginning research, through design and delivery to customers.

Work History

Jun 2015Present

FPGA Engineer

Pentek Inc
  • Reworked a Xilinx ISE FPGA project to add a timing delay feature for legacy customers
  • Designed Pentek's first Ethernet based device using custom VHDL logic & Xilinx IP cores
  • Researched how to implement and design ethernet controller according to IEEE spec
  • Simulated Ethernet using model sim to workout early bugs in design
  • Closed timing setup, hold, and pulse width errors using constraints & design changes
  • Debugged Logic in FPGA hardware using Xilinx chipscope in real time
Jun 2013Feb 2015

Engineer, System Z

  • Developed an emulation design of future System Z, I/O ASIC in a small team.
  • Used VHDL to create logic designs to emulate IBM memory arrays.
  • Created Linux shell script to streamline the process of building, simulating, and verifying the 300+ array designs.                                                                                                              
Jun 2012Aug 2012


Ford Motor Company
  • Created circuit diagram and documentation for car interior Heads-up Display which   displays fuel economy to the user.



Bachelor of Science in Electrical Engineering

Temple University

GPA: 3.74
Awards and Honors: Magna Cum Laude, Temple University Honors Program, Eta Kappa Nu- Iota Sigma Chapter, 2011 IEEE PES Scholar, 2012 IEEE Region2 Ethics Award, 2012 IEEE Philadelphia Section Leadership Award, 2012 HENAAC Scholar, 2012 Temple College of Engineering Award



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