Lead Hardware Engineer, System Verification Group
Advanced Verification Methodology
- Led the implementation of a sophisticated, object-oriented, constrained-random, coverage-driven, SystemVerilog verification environment for multiple large-scale, high-speed FPGAs. The FPGAs were part of a complex router line card development designed to handle traffic speeds up to 60G Bytes/sec. This was an ASIC level verification effort performed on an FPGA based system.
- Key contributor to the new verification strategy by architecting the VMM test bench environment. Also guided team through the development by writing test plans, creating slides and presenting advanced test bench tutorials and information sessions to the team to increase the group's knowledge base.
- Led the deployment of an assertion based methodology including adding SystemVerilog Assertions to both the test bench and chip domains.
- Utilized Perl to develop automated scripts for regression runs using a distributed load sharing utility. Created scripts to help merge and analyze coverage data and archive regression results. Used wiki to track status of verification progress.
Successful Off-Site FPGA Verification
- Lead development engineer for a functional verification project involving two Verilog based FPGAs on a state-of-the-art router line card project (Redback SE1200). Design and verification teams were on separate geographic sites.
- Created Vera and Verilog based bus functional models and test bench environment to stimulate and monitor chip behavior. Also created exhaustive test plan documents and tracked and reported status through a common wiki interface. Executed test plan through a directed test methodology.
- Results proved to be excellent as the FPGAs performed error free during the faster than normal board bring up phase and beyond. Our verification group was singled-out and recognized by the company for outstanding results and extra effort on this project.
Innovative FPGA Design
- Led a Verification IP (VIP) Development project for FPGA based boards or systems. The in-house developed VIP was utilized in place of the full-feature FPGA logic during the board bring up, diagnostics, manufacturing, and IP core validation stages of development.
- Created a project independent library of VIP blocks that provide unique stimulus control and visibility at each FPGA interface. Blocks included generic traffic stimulus and collection modules, internal and external RAM test modules, and traffic rate limiter modules among others.
- Results were great as board-bring up engineers were able to quickly isolate and identify any board problems (such as signal-integrity issues, cross-talk problems, etc.) using the VIP FPGA loads before the full-feature FPGA releases were available.
Development Process Improvements
- Member of a selective cross-functional team of experts tasked to create a more efficient product development process. Created documents for the ASIC/FPGA Simulation Flow Specification. Contributed to specifying the new fault tolerant design and test requirements.