Michael Berty

Michael Berty


  • Verification and design expert.
  • 10+ years experience in verification and design of cutting edge high-speed ASICs and FPGAs.
  • Multifaceted engineer with a wide breadth of knowledge and experience in product development cycle.
  • Experience with the most advanced verification methodologies.
  • Proven track record of successful results from complex projects including 8 ASIC designs and 15+ large-scale FPGA designs.
  • Demonstrated ability to set and reach aggressive and challenging goals.
  • Excellent communication skills and a thirst for increased knowledge of new technologies.

Technical Skills

  • Hardware Description Languages: Verilog, VHDL
  • Test bench Languages: SystemVerilog, Vera, SystemVerilog Assertions (SVA), Advanced VMM test bench methodology.
  • EDA Tools: Synopsys VCS, Mentor ModelSim/QuestaSim, Synplicity synthesis tool, Altera FPGA flow.
  • Programming and utility: C/C++, UNIX shells programming, Perl.
  • Protocol concepts: IPv4, IPv6, Ethernet, LLC/Snap, MPLS, PPP TCP, ATM, AAL5, etc.
  • Interface experience: XAUI, SPI4p2, SPI4p1, GMII, RGMII, PCI, 8B10B, POS-3, Utopia 1-3, proprietary high-speed.


  • Ericsson - "Spirit of Doing Things Better Award" May, 2008 - for extra effort and great performance results during Redback SE1200 project.
  • Ericsson - "Special Achievement Award" Feb, 2007 - for outstanding individual performance.
  • Marconi - "Team Excellence Award" Apr, 2003 - lasting contributions during OC192 ATM Portcard and BXR-48000 projects.


To become a key contributor on exciting, state-of-the-art software and/or hardware engineering projects requiring a variety of technical skills.

Work History

Work History
May 2004 - Present

Lead Hardware Engineer, System Verification Group


Advanced Verification Methodology

  • Led the implementation of a sophisticated, object-oriented, constrained-random, coverage-driven, SystemVerilog verification environment for multiple large-scale, high-speed FPGAs. The FPGAs were part of a complex router line card development designed to handle traffic speeds up to 60G Bytes/sec. This was an ASIC level verification effort performed on an FPGA based system.
  • Key contributor to the new verification strategy by architecting the VMM test bench environment. Also guided team through the development by writing test plans, creating slides and presenting advanced test bench tutorials and information sessions to the team to increase the group's knowledge base.
  • Led the deployment of an assertion based methodology including adding SystemVerilog Assertions to both the test bench and chip domains.
  • Utilized Perl to develop automated scripts for regression runs using a distributed load sharing utility. Created scripts to help merge and analyze coverage data and archive regression results. Used wiki to track status of verification progress.

Successful Off-Site FPGA Verification

  • Lead development engineer for a functional verification project involving two Verilog based FPGAs on a state-of-the-art router line card project (Redback SE1200). Design and verification teams were on separate geographic sites. 
  • Created Vera and Verilog based bus functional models and test bench environment to stimulate and monitor chip behavior. Also created exhaustive test plan documents and tracked and reported status through a common wiki interface. Executed test plan through a directed test methodology.
  • Results proved to be excellent as the FPGAs performed error free during the faster than normal board bring up phase and beyond. Our verification group was singled-out and recognized by the company for outstanding results and extra effort on this project.

Innovative FPGA Design

  • Led a Verification IP (VIP) Development project for FPGA based boards or systems. The in-house developed VIP was utilized in place of the full-feature FPGA logic during the board bring up, diagnostics, manufacturing, and IP core validation stages of development.
  • Created a project independent library of VIP blocks that provide unique stimulus control and visibility at each FPGA interface. Blocks included generic traffic stimulus and collection modules, internal and external RAM test modules, and traffic rate limiter modules among others.
  • Results were great as board-bring up engineers were able to quickly isolate and identify any board problems (such as signal-integrity issues, cross-talk problems, etc.) using the VIP FPGA loads before the full-feature FPGA releases were available.

Development Process Improvements

  • Member of a selective cross-functional team of experts tasked to create a more efficient product development process. Created documents for the ASIC/FPGA Simulation Flow Specification. Contributed to specifying the new fault tolerant design and test requirements.
May 2000 - May 2004

Senior Hardware Engineer, System Verification Group

Marconi Communications/FORE Systems

Large Scale ASIC and System Verification

  • Major contributor of a small team of engineers focused on the system verification of the BXR-48000 (scalable 480G Broadband Switch Router) project.
  • Responsibilities included implementation of the highly-configurable, in-house developed simulation test bench. Pushed the limits of the VHDL language to create powerful stimulus, collection and automatic data checking capabilities. Developed advanced test bench features such as fault insertion, random testing, and bandwidth characterization capability.
  • This highly configurable test bench architecture allowed ASIC designs to be simulated at a chip level, multi-chip level, and full system level. 
  • Helped create a distributed simulation environment to facilitate simulations of the entire system at once. This work resulted in a Mentor Graphics success story press release.

Full Board Simulation Process

  • Member of team that created an efficient process and methodology to translate board schematics into full system simulations.  The process is used to convert a board netlist to a VHDL based simulation. Utilized Perl to create scripts to perform the low-level conversion functions.
  • This process has been used on the most-complex board designs with great success. Multiple problems that would have caused board re-spins were uncovered early in the design phase by utilizing this board simulation process.
Jun 1998 - May 2000

ASIC Development Engineer, ATM Core Switch Hardware Division

FORE Systems

ASIC Design

  • Designer of custom built register controller interface modules for two high-bandwidth ATM port card ASICs. Created Behavioral Design Specification document and Architecture Design Specification document for these blocks. ASICs were Lucent .25 micron CMOS technology, 100 MHz (300K and 370K logic gates). Performed RTL design, verification, and integration into larger chip for these blocks.
  • Experienced first pass success for these two ASICs.

ASIC Verification

  • Key contributor to the verification effort on a very large next generation non-blocking switch/router that scales up to 480G bytes/sec.  This system contained multiple instances of 5 different multi-million gate ASICs.  Utilized VHDL and the FLI to create a simulation environment for each of the 5 ASIC designs including automatic data checking capabilities. 
  • Member of a team of engineers responsible for the functional verification of two high-speed complex ATM port card ASICs. Created bus-functional models for various traffic and control path interfaces for the ASICs. Developed automatic data checking capability for each chip interface. Created documentation for high-level test bench usage and contributed to verification test plans. Executed test plan by writing directed tests for various features of each ASIC. Also ran full gate-level simulations of each ASIC. Created test vectors for the ASIC foundry to use to validate each chip.


May 1996 - May 1998

M.S., Electrical and Computer Engineering

  • Masters research with the CMU Center for Silicon System Implementation
  • Research focus: Low power embedded RAM design.
  • Masters Thesis: Exploring Low Power Memory Design
  • http://www.ece.cmu.edu/research/publications/1998/CMU-ECE-1998-018.pdf
Aug 1992 - May 1996

B.S., Electrical and Computer Engineering, Minor in Environmental Engineering

  • Minor in Environmental Engineering



Tim Noh

Worked under Tim in a leadership role in the System Verification group.