Doctor of Philosophy - PhD
North Carolina State University
I am a Power Analysis/correlation engineer with 10 years of experience in low-power design, pre-silicon RTL and gate power analysis, and post-silicon correlation. In addition, I have expertise in FPGA and embedded design as well as hardware reverse engineering and reverse-engineering protection via my research and PhD experience at NC State University. I consider myself a "maker" and enjoy staying plugged in with the maker community and advancements in robotics, autonomous drones, and control systems.
A Novel Approach To IP Protection Using Automated Hardware Level Techniques To Secure A Design. (Mar 30, 2012)
Dissertation focused on IP protection of ASIC designs. Primarily focused on RTL-based digital designs, it explores using encryption of state machines combined with keys to obfuscate and protect the design from reverse engineering. Briefly covers various methods that can be used to reverse engineer silicon hardware. (PDF Link)
A Scalable Architecture For Hardware Acceleration of Large Sparse Matrix Calculations (Aug 1, 2007)
FPGA focused work looking at acceleration of large matrix multiplication using reconfigurable hardware. (PDF Link)