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Summary

I am a Power Analysis/correlation engineer with 10 years of experience in low-power design, pre-silicon RTL and gate power analysis, and post-silicon correlation. In addition, I have expertise in FPGA and embedded design as well as hardware reverse engineering and reverse-engineering protection via my research and PhD experience at NC State University. I consider myself a "maker" and enjoy staying plugged in with the maker community and advancements in robotics, autonomous drones, and control systems.

Education

20072012

Doctor of Philosophy - PhD

North Carolina State University

Computer Engineering

20052007

Masters

North Carolina State University

Computer Engineering

Skills

Hardware ASIC - VLSI Design
  • Mobile and Server focused System on Chip design (SOC)
  • FPGA and embedded design
  • Hardware Debug by standard test equipment, JTAG and limited rework
  • RTL verification using UVM-based testbench
  • Strong Verilog, SystemVerilog skills, exposure to VHDL and SystemC
Software Development
  • Familiarity with all major OS platforms.  Strong Linux familiarity, use ArchLinux as my daily driver.  Familiar with linux kernel structure, configuration and compile flow.
  • Experience with GNU toolchain and gdb debugger in software design flow.
  • Experience with git, svn, repo and perforce based source control systems
  • Python and shell scripting experience from design flow creation and extension work.
  • low-level driver and firmware experience using C.  Familiarity with UEFI and BIOS boot flows, customization and design.  Experience customizing RTOS environments during embedded design work
  • Strong Object-Oriented design experience in C++ and Java
Silicon Power Analysis
  • Extensive RTL power analysis experience using both PowerArtist and PowerPro.
  • Knowledge of low-power design coupled with power reduction analysis during design flow.
  • Expertise in Gate-level power analysis by PTPX with gate-level and RTL-level sims
  • Expertise in post-silicon power correlation by creation/use of targeted test cases and execution of industry standard benchmarks.
Hobbyist knowledge
  • IT interest and experience in network design, configuration and management including use of enterprise-level protocols
  • Experience setting up and managing virtualization environments using ESX, KVM and XEN.
  • Strong Interest in robotics and control systems from my involvement/following of maker community and home automation.
  • Industrial Automation experience from several years experience working in pharmaceutical plant.  Exposure and experience with ABB, DeltaV, one-line diagrams, ladder-logic, VFD configuration, and DeltaV mimic emulation platform.
  • Machine-learning interest and experience using the free-level of both Google Cloud Platform and Amazon Web Services platform.

Work experience

06/200505/2009

Intern

Talecris Biotherapeutics, Inc (a.k.a Griffols Inc)
  • Aided power plant distribution engineers to create a centralized database to track and provide details from all power distribution panels across the plant
  • Coordinated with on-site IT team to deploy database on central server and set up user interface with multiple access levels available
  • Developed high-level ladder logic plan from field observations and studying the existing program, which was further developed by control system programmers into a modern control system program
05/200804/2018

Staff Engineer

Qualcomm Datacenter Technologies
  • Developed competency and became core contact for team in RTL power analysis for most of the IP integrated in our SOC.
  • Developed expertise using PowerArist, PowerPro, and PTPX for doing RTL and gate-level power analysis on a variety of mobile and server IP cores.
  • Guided teams through power reduction of their IP and assisted with interpretation and use of power reduction results.
  • Wrote custom RTL files to wrap around some RTL-hybrid-custom design structures to allow power measurements at RTL level and for simulations to pass and successfully map to the corresponding RTL. This also involved writing a custom scripts to run on the RTL before power analysis and adaptation of existing design flows to work with modifications.
  • Created and executed tests to measure and correlate power measurements.
  • Served as lab lead for our team maintaining and acquiring test equipment and resources necessary for us to run and measure power on our early development hardware.
  • Setup SNMP monitoring system to track and measure non-power related statistics related to our platforms such as fan speed, firmware versions loaded, frequency and voltage operating points and temperature.
  • Provided power debug support for post-silicon power issues identified in field and lab. Identified root causes for various power bugs and in-rush current issues by running targeted test cases while measuring power and analyzing results.
  • Experience analyzing silicon power at controlled temperatures and simulated operating environments via use of Thermal ovens and Temperature Control Units.
  • Executed silicon power measurement and characterization focused on server benchmarks including SPECint, SPECfp, SPECpower, and Dhrystone.

Publications

A Novel Approach To IP Protection Using Automated Hardware Level Techniques To Secure A Design. (Mar 30, 2012)

Dissertation focused on IP protection of ASIC designs. Primarily focused on RTL-based digital designs, it explores using encryption of state machines combined with keys to obfuscate and protect the design from reverse engineering. Briefly covers various methods that can be used to reverse engineer silicon hardware. (PDF Link)


A Scalable Architecture For Hardware Acceleration of Large Sparse Matrix Calculations (Aug 1, 2007)

FPGA focused work looking at acceleration of large matrix multiplication using reconfigurable hardware. (PDF Link)