Karthikeyan Krishnamourthy

Karthikeyan Krishnamourthy

Work History

Work History
Jun 2014 - Aug 2014

Intern

ALSOC, SoC department, LIP6 laboratory, UPMC
The work was a part of a European project called as TSAR (Tera-Scale Architecture) in the framework of MEDEA. This internship was devoted to the “Comparison of arbitrage strategies in a router-on-chip: Round Robin VS First-Come-First-Served”. Detailed information about the project, the role that I played and the obtained results are explained in the project section.
Feb 2013 - Jun 2013

Research Intern

Universitat Politècnica de Catalunya
Worked on a Public Research project "Micro Electro Mechanical System on Chip (MEMSoC, TEC2011-2704)", funded by the Spanish Ministry of Science and Innovation For Advanced Hardware Research Group, Department of Electronics Engineering, UPC Barcelona. • Implementation of a scalable Bio-inspired Vector processing architecture for Spiking Neural Networks Emulation
Jan 2012 - Jan 2013

Research Assistant

SASTRA University
Worked in VLSI Info-Security group in developing and implementing various algorithms & architectures for Random digital Image Steganograhy. • FPGA Implementation of fortuitous Colour Image Stego algorithms using Cyclone-II - Altera DE1. • Hi-speed embedding, Hardware consumption and the error metrics such as MSE and PSNR have been investigated.

Education

Education
2013 - 2015

Master of Science (M.Sc)

Linköping University

Skills

Skills

PSpice

LabVIEW

Cadence Virtuoso Layout Editor

HDL Designer

ModelSim

Chipscope

Verilog-AMS

Verilog

Cadence Spectre

TCL

Steganography

Xilinx Vivado

Computer Architecture

Pspice

VHDL

Cadence Virtuoso

Simulink

Altera Quartus

Cryptography

Xilinx ISE

Labview

Keil

C++

VLSI

C

Matlab

FPGA

Embedded Systems