Jithesh C P

Jithesh C P


Aug 2003 - Jul 2005


National Institute of Technology
  • Course qualification: Secured first class with a score of 8.32 CGPA on 10 point scale
  • Course project: FPGA based implementation of self-timed FIR filter
Aug 1998 - Jul 2002


NSS College of Engineering
  • Course qualification: Secured first class (honors) with a score of 79 percentage
  • Course project: Microcontroller Based Satellite Dish Positioning System

Work History

Work History
Jan 2011 - Present

Assistant Professor

Government Engineering College, Kozhikode

Government Engineering College, Kozhikode is one among nine government engineering colleges in kerala under the department of technical education run by the Govt. of Kerala started in 1999 with four departments i.e. Civil Engineering, Mechanical Engineering, Electronics Engineering and Chemical Engineering offering 4 Year B.Tech and 2 Year M.Tech courses in respective disciplines. Department of Electronics offers two UG programs B.Tech Applied Electronics & Instrumentation Engineering, and Electronics & Communication Engineering (started in 2012) and one M.Tech program in signal processing. For more details, please visit www.geckkd.ac.in. I am working as Assistant Professor in the department of Electronics (reporting to Head Of the Department, Dept. of Electronics) whose role is to handle lecture hours for UG/PG semesters, Staff Advisor for UG, Academic project guide, Assist department and college level academic and or cultural activities


  • Handle Two Theory and One practical subject with an average workload of 14 hours/week for B.Tech and M.Tech in every semester
  • Faculty-in-charge for microprocessor lab responsible for managing equipment purchases for the academic lab and project activities by utilizing state and central govt. Funds
  • Department Academic Co-ordinator for executing departmental periodic B.Tech series test, maintain record of in-house and external faculty training programs and prepare reports of various academic activities from time to time as requested by higher authorities
  • Staff advisor for the first ECE batch to maintain the academic student record and serve as point of contact for the batch student academic concerns
  • University Examiner for end semester theory and practical examination and or thesis/viva-voce/project evaluation
  • IPR cell college level co-ordinator to act as interface to Patent Information Cell, Kerala and the institute to manage IPR related activities i.e. publish news letter and update in college notice board, communicate workshop, seminars conducted related to IPR to college faculty and students to create awareness on intellectual property rights

Keywords: Lecturer,Bachelor of Technology,Master of Technology,academic course, teaching, semester, project guide, engineering semester evaluation,university examiner, staff advisor,academic-coordinator


  • Prepared Proposal and executed procurement of embedded boards and software packages amounts to 9 lac for the microprocessor lab through AICTE fund in the year 2012-13
  • Prepared proposal and completed procurement of equipments for an amount of ~5 lac through TEQIP Phase-II fund in 2012-13
  • Prepared department level academic proposal with cost budget of 30 lac for the year 2013-14 for utilizing the TEQIP fund
  • Successfully co-ordinated THREE short term training programs related to Digital Design, Power Electronics, E-Waste managment during the year 2011-2013
  • Guided 7 UG level and 3 PG level academic projects related to VLSI domain till date and mini-project co-ordinator during 2012-13 academic year
Jun 2007 - Jul 2010

Component Design Engineer

Intel Corporation

Intel Corporation is a leading semiconductor MNC for computer hardware and consumer electronic products, HQ in California US. For more details, please visit www.intel.com. I was part of Enterprise Microprocessor Group at Intel Bangalore design centre as a design automation engineer (reporting to Engineering Manager) whose role is to develop, integrate and manage the pre-silicon design validation software flows and tools for various server-class (Intel Xeon) CPU products as well as integrated graphics for future generation client CPU products


  • Evaluate, integrate and manage front end pre-silicon design environment and EDA tools for Intel Xeon Server CPU design/Client CPU and graphics projects
  • Serve as key design automation/CAD support engineer for hundred member CPU design team at site and few cross site teams in US
  • Collaborate with cross site functional teams for design methodology and or EDA tool improvement initiatives
  • Co-ordinate and manage compute infrastructure for CPU design team at site
  • Collaborate with Electronic Design Automation vendors for third party EDA solution evaluation and training

Keywords: Front-end RTL design automation, CAD, EDA Tools, Pre-silicon validation methodologies, Intel Xeon Server CPU, Intel Integrated Graphics, Intel architectures, design infrastructure and compute, EDA license management, Version control software management, RCS, Bitkeeper, compilers, simulators, software debugger, profilers, performance optimization, VCS, Specman, Verdi, silotti, Debussy, Verilog, System Verilog, Assertions, Specman e, C++, Modelsim, 0-In, Perl, UNIX,LINUX, gdb, csh, shell scripting


  • Excellent track record in managing design automation environment for the design activities of Intel’s 6-core, 8-core and 10-core Xeon Server products acknowledged by multiple individual recognitions
  • Received site level recognition (Intel Honors) for cutting down project infrastructure cost by 3M USD by deploying cost efficient compute solutions during Intel’s 10-core Xeon design development
  • Deployed 1.2x logic simulation speed-up for Intel Xeon design project and 3X speed up for Client Graphics project team by collaborating with EDA Vendor Synopsys Inc.
  • Successfully proto-typed VCS (Synopsys Inc. logic simulator) multi-core technology to benefit Intel’s future CPU and client graphics simulation methodologies
  • Architected novel solution named ‘XpressDebug’ for faster pre-silicon design validation convergence and published as a paper in Intel design technology publication group
Jul 2006 - May 2007

Design Engineer

Freescale Semiconductor

Freescale semiconductor MNC is offshoot of Motorola Inc. hardware group having HQ at Austin, US and focus on providing semiconductor solutions in the areas of mobile, wireless networking and automotives. For more details, please visit website: www.freescale.com. I was part of wireless group at Delhi design centre as a design engineer (reports to design manager) whose role is to validate wireless architecture (IP) for next generation mobile products  


  • Validate USB2.0 IP Physical Layer at module and system level for SoC wireless mobile architectures
  • Own and execute specific software IP test suite in a five member team
  • Document test plan and create protocol test suit for USB2.0 PHY IP software verification and review with project team
  • Find software IP design bugs and close with IP owner in timely fashion

Keywords: VCS, Debussy, NCSIM, Clear Case, IP Standalone Verification, High Speed ULPI & UTMI, USB 2.0 PHY, Functional IP verification, RTL design, Verilog, Vera, USB Link Layer, Synopsys Device BFM, Core Interface, C, USB Driver, RTL gate level simulation

Project: Standalone RTL verification of High speed ULPI and UTMI USB 2.0 PHY modules 

  • Tools: Synopsys VCS, Novas Debussy, Cadence NCSim, Clear Case (Solaris Platform)
  • Duration: 5 Months
  • Role: Setup the test bench environment for IP level functional verification, Write test cases in verilog and vera to verify the protocol functionalities of PHY modules in a standalone environment
  • Description: Module level complete protocol verification of USB High speed physical layer interface in UTMI and ULPI mode along with USB Link layer, Device BFMs and Core Interface 

Project: SoC level RTL and gate level verification of High speed USB 2.0  PHY module

  • Tools: Synopsys VCS, Novas Debussy, Clear Case (Solaris Platform)
  • Duration: 3 Months
  • Role: Write test cases in verilog/C and verify the functionality of  PHY at RTL level and gate level
  • Description: Chip level RTL verification of the USB PHY using Synopsys VCS and Novas Debussy tools. Written the test cases in C (USB driver) and in verilog using BFM and USB PHY RTL modules. Ported passing USB PHY test cases to verify timing violations that could happen at the gate level


  • Worked on System level (SoC) logic and gate level verification of USB2.0 PHY IP for two product tapeouts
Jul 2005 - Jun 2006

Senior Engineer

Tata Elxsi

Tata Elxsi is part of Tata Group of Companies in India providing customized design solutions in the field of consumer electronics, entertainment, media and telecom across globe. For more details, please visit website: www.tataelxsi.com. I was part of Canon Inc. Offshore Design Centre team under the supervision of Senior Design Manager, Hardware&Systems group at Bangalore 


  • Digital IP modelling engineer for serial interface protocols USB2.0/IEEE1394 (fire-wire)
  • Understand protocol specification, software modelling and validate through logic simulation
  • Document and archive the IP and signoff with respective IP integration leads

Keywords: Modelsim, CVS, Digital Modeling, 1394 PHY, TI 1394 Serial Bus PHY TSB41AB1, Verilog, USB2.0 PHY, ULPI, UTMI Macro Cell, Functional Verification 

Project: Modeling the Physical Layer (1394 PHY) of 1394a protocol

  • Client: Canon Incorporated, Japan
  • Tools: Mentor Graphics Modelsim and winCVS
  • Duration: 5 Months
  • Role: Verilog Coding and stand alone verification of the PHY module
  • Description: Digital Modeling of the 1394 PHY one port transceiver module for interfacing 1394 Link controller using Texas Instruments 1394 serial bus PHY-TSB41AB1 as a reference model

Project: Modeling the Physical Layer (ULPI v1.1) of USB 2.0 protocol

  • Client: Canon Incorporated, Japan
  • Tools: Mentor Graphics Modelsim and winCVS
  • Duration: 4 Months
  • Role: Verilog Coding and stand alone verification of the ULPI module
  • Description: Digital Modeling of the USB transceiver macro cell module (UTMI+ low pin interface) for interfacing USB Link controller. Ensure functional correctness of USB 2.0 RTL


  • Delivered Physical layer IP behavioral models for serial interface protocols USB2.0 and IEEE1394 which funded by client Canon Inc. Japan for Tata Elxsi Bangalore 



software langauages: C/Perl

Verification test case development using C for USB IP at Freescale semiconductor Perl based scripting expertise for tool and database management automation at Intel Corporation C based simulation environment expsoure for VCS/Specman PLI interface at Intel Corporation

platforms: UNIX/LINUX/Windows

Multiple project experience through pre-silicon validation and database managment softwares on UNIX/LINUX(Redhat and SUSE) platforms Handson expertise on revision control repository managment (Bitkeeper, RCS, perforce, clearcase) in UNIX environment Handson expertise on EDA tool and license management in UNIX environment UNIX based shell scripting expertise for project database management

HDL/HVLs: Verilog/System Verilog

Verilog HDL modeling experience for serial interface protocols USB/IEEE1394 Verilog RTL verification experience for USB2.0 PHY at Freescale semiconductor System Verilog use model experience in CPU and graphics design environment as a design automation engineer at Intel

EDA Tool: Mentor Graphics Modelsim/0-in

Digital modeling project use model experience with modelsim at Tata Elxsi 0-in assertion use model experience in CPU pre-silicon design verification environment at Intel Corporation 0-in support engineer for Intel CPU design team where filed one bug on tool during the course Department level award for successful completion of pilot work named 0in2SVA (methodology for migrating legacy 0-in assertions to System Verilog Assertions) to save compute license cost for the Bangalore CPU design team at Intel

EDA Tool: Cadence Specman

Expertise as a tool methodology engineer for Cadence specman at Intel Corporation  where dealt with tool version enhancement evaluation and performance optimization for CPU and Graphics design environments Good understanding of specman tool use model in pre-silicon validation environment including simulator setup Received department level recognitions for specman tool debug and environment bring up support activities Enrolled in Intel specman technology group for performance and tool enhancements collaborating with Cadence Inc.

EDA Tool: Novas Verdi

Served as CAD support engineer for Verdi/Debussy debugger solution including tool support and evaluation activities for Intel CPU and Graphics design team in Bangalore and US Hands-on expertise on verdi/debussy use models for pre-silicon verification debug activities through multiple projects at Freescale semiconductor and Intel Corporation

EDA Tool: Synopsys VCS

Good knowledge of Synopsys VCS simulator use models (RTL compile&simulate and code coverage) in CPU/SoC pre-silicon validation environment Dealt with serial and multi-core performance  (PVCS) optimization for simulator speed up initiatives collaborating with Synopsys Inc. team Work experience with Intel-Synopsys VCS technology group for simulation performance improvement activities across design projects Expertise as VCS support engineer for CPU and Graphics projects at Intel where filed multiple tool bugs with Synopsys Inc. Bangalore    

Personal Info

  • Date Of Birth: 12th March 1980
  • Gender: Male
  • Marital Status: Married
  • Nationality:  Indian
  • State of domicile: Kerala
  • Languages Known: Malayalam, English, Tamil, Hindi
  • Passport No: J3859140(india)
  • Driving License No: M/3028/2000 (India)

Career Objective

Seeking a challenging full-time opportunity in the areas related to consumer electronic product design, VLSI/semiconductor IC design, EDA methodology solution or in the academic field as professor in relevant subject domain

Awards and Honors

  • Honors degree in engineering from Calicut University in 2002
  • Certificate of Merit for securing 1st Rank in class during B.Tech course
  • GATE-2003 scholarship qualified with score 96 percentile
  • Multiple recognitions from Intel Technolology India for performance achievements


  • Technical interests: VLSI EDA tools and methodologies, software simulator technologies and performance optimization, IP pre-silicon design validation and debug solutions
  • Personal interests: Professional networking, Listnening to music, Travelling, Reading dailies

Professional Profile

A post graduate in VLSI design technology with 3+ years in academic field and 5 years of industry experience in electronic design validation, EDA tools and methodologies for ASICs, SoCs and CPU products

  • Assistant Professor of dept. of Electronics, Govt. Engineering College, Kozhikode (Calicut) taking responsibilities include not limited to staff advisor for UG, Microprocessor&VLSI Lab faculty in charge, Dept.Co-ordinator for TEQIP related academic activities, IPR cell Co-ordinator
  • Design automation engineer for server/client CPUs and integrated graphics products at Intel Corporation
  • USB2.0 PHY IP pre-silicon validation experience at Freescale Semiconductor
  • Digital IP modeling expertise for serial interface protocols like USB/IEEE1394 at Tata Elxsi
  • Digital programming and system prototyping exposure (FPGAs) during Master's course work at National Institute of Technology Trichy
  • Proficient in working with EDA tools Synopsys VCS, Cadence Specman, Novas Debussy/Verdi, Mentor Graphics Modelsim and 0-in
  • Multiple project experience in Verilog, System Verilog, C/C++ and perl based pre-silicon design verification environment
  • Multiple project experience in EDA compute infrastructure planning and support for CPU design platforms
  • Acquired skills to interact with local and cross site stake holders for EDA methodology planning and deployment as a CAD design engineer
  • An innovative self starter and quick learner with excellent written and oral communication skills
  • Ability to work in a group of engineers/technologists and individually in a deadline driven environment

Academic Certifications

Professional Certifications


Jul 2013 - Jul 2013

Embedded System Design

NIELIT Calicut
Apr 2013 - Apr 2013

System Design with DSP

NIELIT Calicut
Mar 2013 - Mar 2013

Data Acquistion and Control

NIELIT Calicut
Jan 2012 - Jan 2012

Development of life skills (STP1023/11)

IMG Calicut
Jun 2009 - Jun 2009

Career training: Influence Edge

Intel Corporation
Mar 2006 - Mar 2006

System Verilog Training

Synopsys India Pvt. Ltd.