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Work experience

Jun 2010Present

Sr.Staff Design and Verification Engineer

Rapid Bridge

+ Integration, verification, design of hard & soft IP subsystems & complete solutions: Mixed-signal, digital, sea-of-gates using metal-programmable Gate Array kits (32nm and below)

+ Turn-key chip development, from concept to packaged silicon

+ Applications vary from computing, to networking, to wireless, to pre and post-sale customer support

Achievements: Key developer and customer-facing liaison for one-of-a-kind, patented die Speed-Yield-Power tuning solution that won the biggest contract in the company history

> Completed refresher training in Synopsys Design Compiler and Prime Time SI

Mar 2009Jun 2010

Senior Consultant


+ FPGA design, verification, tool flow, implementation. Interface to system, electrical, analog, PCB & FW teams + Xilinx Virtex5 (SXT240, LX220, SXT50, LX50) with ISE11sp4. Altera CPLDs with Quartus II 9.1 + VHDL and SystemVerilog-2009 with OVM2.1 on Mentor ModelSim 6.5d and Cadence Incisive 8.2 + Applications includeSBC/COTS, industrial/military PC, image grabbing, PCIe, LPC/SERIRQ, DMA, SRIO, FMC

Achievements:  Developed HDKs, integrated IP into and built custom apps on top of them. Processed data from 3GSPS ADC and implemented DSP algorithms in FPGA. Created custom SuperIO controller for the 32nm Intel i7 Calpella mobile Xpress platform in a rugged VME/VPX form-factor with X/PMC sites. Interfaced to Xilinx PCIe and Aurora macros on one side and driver firmware on the other

> Completed Intel MindShare training in PCI Express, including Gen2.0 additions

> Completed Altera training in Quartus II tool suite, C2H and PCIe on Arria2GX FPGAs

Jul 2006Mar 2009

Principal Engineer


+ ASIC/SoC lead. RTL design and verification. Liaison to IP vendors, FW, PnR, analog & DSP/Sys teams + TSMC 65nm, 90nm, 130nm nodes in COT flow + Synopsys DC-Ultra. PrimeTime SI. Build scripts, constraints, timing closure. SDC, TCL, Perl, CSH + SystemVerilog-2005 with AVM on Mentor QuestaSim. Synopsys VCS for gate-level. Mentor Precision RTL + Applications include DDR2/3 SDRAM controller+PHY, 8051 with AMBA APB3, MoCA, 4x10GbE PHY, MDIO

Achievements: Architected standards-based, modular control plane for a 4-million gate ASIC. Devised transparent, hardware-accelerated 8-to-16 bit bridging which boosted firmware throughput so that a low-end, 8-bit micro sufficed. Automated CSR generation using Perl. Wrote APB transactors in SV and device drivers in Keil AX51 & C51.

Evaluated, procured and used IP for DDR2/3 SDRAM controller (soft) and PHY (hard). Worked with vendors and created SOW + I/F spec. Wrote DC synthesis and PTSI sign-off scripts in TCL/SDC. Guided the P&R towards timing closure. Worked with Product and Test Engineering to characterize the IP, which then integrated in the (AXI-based) SoC.

Led prototyping of a cable modem (MoCA) in a Virtex4 LX200 FPGA with discrete OFDM RF stage on a separate board. Baseband processing included MAC with QAM2to256 data pump. Designed on-chip PowerPC 405 embedded subsystem with DMA-enabled packet buffering. PPC ran the MAC layer (soft, in firmware) and DSP coefficient management.

> Received performance-based awards

Oct 2000Jun 2006

Staff Engineer

Copper Mountain Networks (then TUTS, now Motorola)

+ FPGA/pSoC lead: Architecture, RTL design, verification. Methodology, scheduling/planning, mentoring + Xilinx Virtex2, Virtex2Pro, Spartan3, Virtex4 with 3.125GBaud SerDes and on-chip PowerPC405s + Verilog with OVA. ModelSim. Synplicity. EDK Platform Studio + Applications include dataplane fabric & post-processing for telco-grade IPTV delivery/access node platform

Achievements: Architected as a library of parameterized & reusable modules, the Fabric spanned some 20 distinct FPGA designs distributed across a variety of SerDes-connected Switch, Processor and I/O cards. It contained complex controllers and state machines, in select cases even employing multiple on-chip PowerPC 405 subsystems. It reconciled the disparity of TCP/IP packets, ATM cells, TDM channels & MPEG transport streams. It glued, transformed, parsed headers, disassembled/converged/reassembled traffic threads, classified, priority-routed, flow-controlled, de-jittered, buffered in both on and off-chip RAM.

Interfaced to RF (QAM, AMVSB, QPSK), MTS, 6415 DSP (EMIF with DMA), xDSL, T1/E1, T3/E3, OC3/12/48, IMA, 10/100/1000 Ethernet, QDR SRAM, XAUI, SPI3, Intel IXP2800 CSIX, 1250 IXB/NP, APPI, SBI, POSPHY2, UTOPIA2.

Set-up functional simulation framework with clean, layered structure and comprehensive scope, which paid off in the rapid board bring-up and bug-free final product.

As the lead of a team of 3, defined & instituted FPGA development process for design correctness, re-use, manageability & portability. This resulted in significant time-to-market edge.

Through meticulous analysis of the functions to implement, achieved elegant simplicity and complexity without complication… which opened the gates for doing more in less silicon & so helped the bottom line.

> Received formal training in System Verilog

> Received 'Leader of the Pack Award' for leading by example

> Received 'Certificate of Achievement' for succeeding to accommodate a major last-minute feature change

Jul 1997Sep 2000

Senior Engineer


+ ASIC/FPGA RTL design and verification. Liaison to FW, board and mixed-signal teams + 150nm (all-Cu) IBM ASIC flow with industry-first on-chip SerDes (also packaged as standalone hard IP macro) + Verilog and C. Actel + Applications include carrier-class SONET/SDH core-network node (OC192/768/1536, DWDM)

Achievements: Designed TSI, Framer block and clock control scheme (over 70 domains) with all timing handoffs for an 11-million gate standard-cell ASIC. Served as liaison to 2.5Gbps SerDes macro design team, which then integrated.

Designed FPGA-assisted, software-laden numeric Stratum-3 PLL card. Used an array of Actel FPGAs and Motorola PowerQUICC micro. Wrote all Verilog and some of the C device drivers.

> Received formal training in Verilog, Advanced Verilog, C, Perl, Synopsys VCS, DC, Prime Time, (formerly) Chrysalis Equivalence Checker, Nortel COT flow, Nortel DFT, RF I, RF II, Assertiveness, Negotiations

Sep 1993Jun 1997

Senior Engineer

Gandalf Data Ltd. (now Mitel)

+ FPGA/PLD and circuit/schematics design. Direct interaction with FW, system, test and approvals’ teams + VHDL, AHDL, PALASM, Intel RISC. Lattice, Altera, Mentor, Viewlogic, OrCAD + Applications include edge network datacom/telecom (Terminal Server, Bridge, Router, ISDN PRI, POTS)

Achievements: Developed communications products based on Intel i960CF/HX RISC processor, Lattice (then Lucent) ORCA2C FPGAs, Altera FLEX8K FPGAs, Intel Flash EPLDs and Altera MAX7K CPLD.

> Received formal training in VHDL, Exemplar synthesis, ViewLogic and Mentor Design Architect schematics

May 1989Mar 1993

Design Engineer

Energoinvest / IRCA

+ Logic & circuit design in Able & OrCAD + Intel 80188. Programming in C, ASM86 and PL/M-86 + Applications include ISDN BRI, Industrial Control, AX.25 and UHF/VHF TV transmission




Univerzitet u Sarajevu

+ Graduated with Honors+ Endorsed by:

      ~ US Department of Labor

      ~ University of Toronto, Canada


Ethernet, SONET/SDH, ATM, TDM, POTS, Serial, POTS/Analog
Synopsys DC, PTSI COT, DFT, back-end flow
SoC, Embedded
HW/SW Integration, Bring-up and Debug, Firmware 8051, PowerPC, 80x86, RISC, PowerQUICC, Intel Interfaces, peripherals and ASSPs Xilinx EDK Platform Studio eclipse
Digital Design
Partitioning Architecture, Microarchitecture Logic & Timing Design Simulation/Verification
RTL BFM Self-checking verification, both directed and coverage-driven random-constrained System Verilog with OVM
Xilinx Virtex5, Virtex4, Virtex2P, Virtex2, Spartan3 Altera, Actel, Lattice ModelSim Synplify ISE Xilinx EDK Platform Studio System Generator DSP & Simulink


Shaw Yuan

Shaw's LinkedIn Profile

Jasmin worked with Shaw on DSP aspects of FPGA-based proof-of-concept prototype platform for MoCA cable modem technology

Omer Acikel

Omer's LinkedIn Profile

Jasmin worked with Omer on using FPGAs to accelerate digital and Simulink/MATLAB sims of a DFE/FFE-based CDR block for 10Gbps long-reach SerDes

Portfolio TidBits


  • Formal training in System Verilog, Advanced Verilog and Verilog
  • Formal training in  Synopsys DC, PrimeTime and VCS
  • Formal training in (formerly) Chrysalis Equivalence Checker, Nortel COT flow and Nortel DFT
  • Completed classes in VHDL, Perl
  • Completed classes in RF I, RF II, Mentor Graphics, Viewlogic, Unix
  • Completed classes in Assertiveness, Negotiations
  • Received “Leader Of the Pack Award” for leading by example
  • Received “Certificate Of Achievement” for succeeding to accommodate a major last-minute feature change
  • Received performance-based awards and honors
  • Permanent US Resident and Canadian Citizen


  • 20+ years in digital & embedded space, developing mission-critical & carrier-class electronic products
  • Specialized in FPGA, ASIC, SoC, hardware-assisted computing and micro-architectures
  • High-energy, detail-savvy, pragmatic problem solver with passion for excellence, one who'll take the challenge, embrace the change, keep the customer focus and roll-up the sleeves to make difference
  • Independent in execution, issue clearing, progress reporting, customer, vendor & team interactions
  • Open for consulting and direct hiring

Front-end chip-level developer with solid system perspective

  • Feature, Feasibility, Performance, Trade-off Analysis
  • System Partitioning & Architecture 
  • Interfaces & Handshakes
  • Putting the system together(IP, *RAM, MCU, Peripherals, DDR1/2/3, PCIe, SerDes)
  • Modeling & Functional Simulation
  • Scripting
  • Constraints-driven Synthesis
  • Timing Analysis & Closure
  • Logic & Timing Design
  • RTL Coding
  • Bring-up. HW/SW integration & debug. Lab hands-on
  • Circuit & Schematic Design. Microcontrollers & Firmware. PCB-savvy
  • Chip lead and liaison to third parties


  • Food/Spices/BBQ * Learning & Discovery * Handyman * Gardening * Publishing * Music * History