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Education

Aug 2008May 2010

Masters of Science

The University of Texas at Dallas

GPA: 3.5

Specialization : Digital Systems

Jul 2004May 2008

Bachelor of Engineering

Sri Sairam Engg College, Anna University

Passed out with First Class and Distinction.

Project Experience

RF Circuits and System Design Projects:

Design of Receiver Front End for 4G Wireless Systems using 0.18µm CMOS SALICIDE process:

  • Designed a Dual gain-Low Noise Amplifier with 20dB Gain, 2.05dB Noise Figure, P1dB= -18.5dB
  • Developed a Voltage Controlled Oscillator with Center Freq of 2.15GHz, Phase Noise: 88.63dBc/[email protected]
  • Designed a Direct Down conversion Mixer with 12.15dB Gain, 3.1dB Noise Figure, P1dB= -14dBm.

RF Interference Measurement and Analysis of CC2420 Zigbee RF Transceiver:

  • Programmed Zigbee CC2420 RF Transceiver to tap the Signals at the output of LNA, VGA, and Mixer and the Test signals were viewed from test pins (ATEST 1 & ATEST 2).
  • Measured IIP3 for the given device and effects of the Interference with the two Blockers were analyzed.

Design of Campus Emergency Messaging System:

  • Proposed a Handheld campus emergencydevice that receives and transmits emergency information on campus.
  • Designed System Level Design of two RF Transceivers at 2.4 GHz was using AWR Visual System Simulator Tool
  • Desired Specifications were met and Transmitter depending on the Radiation distance Transmitter power levels were decided

Simulation of simplified LTE OFDM System using Labview:

  • Modulation schemes such as QPSK, 8PSK and 16 QAM were used.
  • A Discrete 3 ray multipath channel model was used and the variation of BER with SNR was analyzed.
  • Calculated the spectral efficiency for different modulation schemes.

VLSI Design Project:

Design of 32 Bit ALU & Control Unit (130nm CMOS Technology):

  • Designed a 32 Bit ALU and control unit (Finite State Machine) using Verilog HDL.
  • Performed DRC, LVS using Cadence, Encounter was used for automatic Placing & Routing.
  • Speed of the Circuit - 3.3ns, No of Cells- 300, Bounding box area: 45516.9 um2.

Microcontroller Projects

Design & Implementation of a Packet Processor using NIOS II soft-core processor.  

  • Altera Nios development system is used to implement CIDR (classless) forwarding engine for IPv4.
  • Quartus & NIOS II IDE was used to design and implement the packet processor.
  • TCAM (Ternary content-addressable memory) was designed for fast look up.

Design & Implementation of  NIDS (Network Intrusion Detection System):

  • ALTERA NIOS II processor was programmed and C Language was used to Design the Algorithm to Detect the Intrusion Worms. The Analyzed Packet and the detected Patterns were stored in the CPU using USART connection.

Data Glove Implementation with Hall Effect Sensors using PIC Micro Controllers:

  • Proposed a Innovative Design of Data Glove System which could to map position of the finger and Identify gestures of American Sign Language. Hall Effect sensors from Allegro Microsystems Inc were used for Mapping
  • Won Best Project Award in Undergraduate Final year Project Exhibit.

Computer Architecture Projects

Implementation of Exclusive Caches using Simplescalar3.0 tool:

  • Performance of the given processor was analyzed using different integer and floating point benchmarks with inclusive cache under various cache size and line width.
  • Exclusive Cache was designed with two different Strategies, Cache behavior was changed to Exclusive by modifying the source code of Simple scalar and the performance difference was studied for the same benchmarks and same cache configurations.

Design of System Architecture that has 512 TByte of Physical Memory for a Single Processor Socket

  • Proposed a design solution to overcome the memory access latency problem while interfacing 512 Terabytes of Main memory to a Uni-Processor.
  • It required a detail analysis of various bus interfaces (PCIe, Hyper Transport), DIMM slot, optical interconnects and various current technologies.

Perl Project

 Automatic Webpage Update Notification:

  • Important WebPages were downloaded using Perl script HTML parsing and Extraction of Required Section was done.
  • The Script Checks for latest updates using Perl Regular Expressions and Intimates the User about the updates.

Objective

To obtain a position that will enable me to use my strong organizational skills, educational background,and ability to work well with people.

Hobbies

Pencil Sketching

Photography

Salsa dancing

Numismatics

Swimming

Interest

ASIC/FPGA Design, Digital Circuit Design, RFIC Design, Microcontroller Design & Programming,Hardware Design

Amateur Projects

About Me

I'm a Person Who strongly believes that  Passion, Hardwork, Patience and Perseverance are the Key to Success.

Summary

RF- Experience:

RF Tuning and Optimization Engineer (UMTS) – Ericsson Inc (Jan 2010 – Aug 2011)

  • Suggested Drive Routes, have analysed TEMS Data in Actix and gave recommendations
  • Troubleshooted RF related issues in Tuning a WCDMA for launch.
  • Automated numerous Redudant work with the help of scripting Languages like Perl and Excel VBA
  • Efficient in Tuning Tools like Mapinfo, Actix (LTE and WCMA), Tems Discovery and Tems Investigaiton.
  • Add and delete appropriate neighbors to create efficient neighbor relations.
  • Worked in some of the challenging markets with toughest terrains.
  • Performed SSV Analysis for WCDMA sites and COW sites

RF Tuning and Optimization Engineer (LTE) – Ericsson Inc (Aug 2011 – Current)

  • Performed Parameter audits.
  • Optimized LTE Networks in GNG Lite Analysis for AT&Tto meet the KPI Requirements
  • Co-ordinated Drive Teams for Site Shakedown
  • Optimization Report Preparation
  • Automated numerous Redundant work with the help of scripting Languages like Perl and Excel VBA

Technical Skills

Design Tools

RF Optimization tools:   Actix, Tems Discovery, Tems Investigation, Map info

HDLs:                            VHDL, VERILOG.

Simulation:                     Modelsim, Synopsys, Cadence, HSPICE, Simvision, SimpleScalar3.0, 

Implementation:             Xilinx ISE 6.3i.

Testing &Optimization:   TetraMax, CPLEX

Embedded Systems:          Intel 8086, Intel 8085 family, PIC 16F and 18F family, SpartanIII (CPLD),

 Oscilloscopes, Spectrum analyzer and In-circuit   emulators.

C compilers:                    Nios II IDE, Mikro C for PIC, Code Composer Studio, Keil, and IAR Workbench.

Skills & Competencies:

Software Languages:      Excel VBA, Embedded C, C, Assembly language, Perl, MatLab, and HTML.

Operating System:  Windows 9X, NT, ME, 2000, Ubuntu, UNIX, Sun Solaris.