Graduate Research Assistant : IC Layout Designer
Integrierte Elektronische Systeme, TU Darmstadt (Germany)
Design of a voltage controlled current source (VCCS) for fiber-to-the-x (FTTx) ASIC. It comprises of current mirrored 2 differential amplifiers and voltage reference. The design is implemented with optimized floor planning and placement with high current density metal layers and vias to minimize the area and increase efficiency. Layout techniques like common-centroid, inter-digitization has been used and DRC, LVS for verification. The SG13S 130nm BiCMOS technology is used in Cadence Virtuoso Layout Design Suite. Currently, post-layout simulations are being carried out.