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Work experience

Jun 2011Present

Principal Engineer and Director of the FPGA Architecture Team

Altera Corporation, aquired by Intel Corporation

Led the architecture team that produced Stratix 10, including Hyperflex pipelined routing, an entirely new software-based methodology for FPGA configuration, and instance-specific neural network proof of concept.

Developed the first implementation of IEEE 1588 time protocol for Altera FPGAs.

Dec 2006Jun 2011

VP of Technology

eASIC

Managed the 18 person off-shore SW team through two major releases. Built the core of the new US-lead Software Team. Maintained the SW tool flow for the 90nm product used in over 100 tapeouts. Coordinated HW and SW teams to architect a 45nm structured-ASIC family (Nextreme-2) based on the lessons of the Nextreme 90nm family. Managed 3rd party EDA vendors, to build a complete software flow for the Nextreme-2. Initiated the development of a standardized IP Library for eASIC. Maintained and refined the eASIC patent portfolio.

Nov 2003Dec 2006

Director, Hardware Architecture

Tabula, Inc

Co-invented much of the companies key technologies.

Determined supported hardware features thru HW/SW experimentation. Negotiated SW feature support and abstractions, and participated in SW feature prioritization. Established simulation and verification methodologies, managed RTL design and verification for successful tape-out of test chip on time. First-time correct silicon.

Sep 1996Dec 2003

Associate Professor

Carnegie Mellon University

Designed and implemented the first true hardware-managed virtual hardware platform: PipeRench. Co-author of the first academic paper on structured ASICs. Author or co-author of over 40 papers and articles. Recepient of the NSF CAREER award and a Best Paper awared at FPL 2003. Program Chair of the FPGA Symposium in 2004. Raised and managed a research budget of approximately $500k/yr.

Aug 1987May 1990

Hardware Engineer

Data General

Worked on the design of the last MV/Eclipse mini-computer. Designed the memory system, including 5 ECL gate arrays that managed split transaction memory access for this multiprocessor. Designed a regular ECC code that could be implemented across four datapath processing gate-arrays. One of the first engineers to use design automation techniques to minimize logic design in the MV/Eclipse Systems.

Education

Sep 1990Nov 1995

Ph.D.

Carnegie Mellon University

Advisor: Donald Thomas

Thesis: High Level Synthesis of Application-specific Memory Systems

19831987

BSE

University of Pennsylvania

GPA: 3.65

Skills

Architectural Trade-off Analysis

In every position I have had, I have worked to design experiments that evaluate different architectural ideas and evaluate their trade-offs in terms of power, throughput, latency, and flexibility. I have done this in multiple domains: for FPGAs (e.g. Tabula and Altera), for microarchitectural features (I-COP), Reconfigurable processors (PipeRench) and Structured ASICs (VPGA and eASIC Nextreme).

Technical Communications / Presentations
Lecturing to brilliant 19-year-old students is a crucible unlike any other for refining communications skills.
Chip Design Flows: RTL Analysis to Tapeout

In 0.18 micron, my team of five students and I taped out first-time working silicon for the PipeRench programmable chip.

In 90nm, I was the lead architect and RTL integration engineer for the first Tabula prototype.

In 45nm, I led the architecture and tools for eASICs Nextreme structured ASIC, including transceivers and DDR memory interfaces.

In 14nm, I led the complete rearchitecting of the Stratix family of FPGAs, resulting in Stratix 10, the first 1GHz FPGA with Hyperflex pipelined interconnect.

Java, C++, Python, Perl

I enjoy programming and building robots in my spare time. I use it as a way to learn about FPGAs, IoT hardware, embedded software, fabrication, machine work, and welding.

My most interesting creation is a drawing robot and the algorithms to render photos that it uses.

Verilog HDL

At eASIC and Altera, I created industrial IP for use on Structured ASICs and FPGAs.

Summary

I like working on complex problems in the boundary between hardware, software, and applications. These problems leverage my key strengths:

  • Understanding the complex dependencies and interactions in HW/SW systems.
  • Spreading that understanding to all team members, regardless of their engineering background.
  • Following up to make sure that those interactions are respected to produce a working system.

After an academic life as a professor at CMU for seven years, I started my Silicon Valley career as one of the founding team members of an ambitious semiconductor startup company. In my three years there, I was co-inventor of the majority of the company's technology. I joined my second startup company right after the announcement of their first product, and participated in the growth of that company from zero to multi-million dollar revenue.

I have managed hardware, software and architecture teams of up to 31  engineers/developers.

One of the talents that I gained in my life as a professor is to understand when and why people do not understand.  I think the most valuable thing I bring to every team is clarity.

Statistics: 45 published papers. 125 granted US patents, working silicon in five different process technologies.

Honors

NSF Career Award 1998

Best Paper Award, Field Programmable Logic Conference, 2001

Winner of the ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award, 2014

For the most influential paper from the International Symposium on Computer Architecture, evaluated 15 years after publication.

FCCM20 Award for my 1997 paper: Incremental Reconfiguration for Pipelined Applications

For one of the 25 most significant papers in the first 20 years of the FCCM Conference.

FPGA20 Award for my 1998 paper: Managing Pipeline-Reconfigurable FPGAs

For one of the 25 most significant papers in the first 20 years of the International Symposium on FPGAs.

Publications

2017

A 14nm 1GHz FPGA with 2.5D transceiver integration

David Greenhill,et al.

ISSCC'17: IEEE International Solid-State Circuits Conference

2016

Stratix™ 10 High Performance Routable Clock Networks

2008

Placement challenges for structured ASICs

Herman Schmit, Amit Gupta, Radu Ciobanu

April 2008

ISPD '08: Proceedings of the 2008 international symposium on Physical design

Bibliometrics:  Downloads (6 Weeks): 6,  Downloads (12 Months): 70,  Citation Count: 1

2005

Layout techniques for FPGA switch blocks

Herman Schmit, Vikas Chandra

January 2005

IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Volume 13 Issue 1

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 2

 2004

A power aware system level interconnect design methodology for latency-insensitive systems

V. Chandra, H. Schmit, A. Xu, L. Pileggi

November 2004

ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Bibliometrics:  Downloads (6 Weeks): 2,  Downloads (12 Months): 19,  Citation Count: 1

Creating a power-aware structured ASIC

R. Reed Taylor, Herman Schmit

August 2004

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Bibliometrics:  Downloads (6 Weeks): 2,  Downloads (12 Months): 15,  Citation Count: 1

Enabling energy efficiency in via-patterned gate array devices

R. Reed Taylor, Herman Schmit

June 2004

DAC '04: Proceedings of the 41st annual Design Automation Conference

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 15,  Citation Count: 2

An Interconnect Channel Design Methodology for High Performance Integrated Circuits

Vikas Chandra, Anthony Xu, Herman Schmit, Larry Pileggi

February 2004

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2 , Volume 2

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 25,  Citation Count: 10

A low power approach to system level pipelined interconnect design

Vikas Chandra, Anthony Xu, Herman Schmit

February 2004

SLIP '04: Proceedings of the 2004 international workshop on System level interconnect prediction

Bibliometrics:  Downloads (6 Weeks): 4,  Downloads (12 Months): 29,  Citation Count: 2

2003

Exploring regular fabrics to optimize the performance-cost trade-off

L. Pileggi, H. Schmit, A. J. Strojwas, P. Gopalakrishnan, V. Kheterpal, A. Koorapaty, C. Patel, V. Rovner, K. Y. Tong

June 2003

DAC '03: Proceedings of the 40th annual Design Automation Conference

Bibliometrics:  Downloads (6 Weeks): 6,  Downloads (12 Months): 68,  Citation Count: 29

CAD TOOL SUPPORT FOR A MULTI-UNIVERSITY SOC CERTIFICATE PROGRAM: THE DIGITAL SANDBOX

Tom Kroll, Herman Schmit, Dave Landis

June 2003

MSE '03: Proceedings of the 2003 International Conference on Microelectronics Systems Education

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 0

The Sandbox Design Experience Course

Herman Schmit, Thomas Kroll, Max Khusid, Ivan Kourtev, N. Vijaykrishnan, David Landis

June 2003

MSE '03: Proceedings of the 2003 International Conference on Microelectronics Systems Education

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 0

Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable

Benjamin A. Levine, Herman H. Schmit

April 2003

FCCM '03: Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 6

Asynchronous PipeRench: Architecture and Performance Estimations

Hiroto Kagotani, Herman Schmit

April 2003

FCCM '03: Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 1

An architectural exploration of via patterned gate arrays

Chetan Patel, Anthony Cozzie, Herman Schmit, Larry Pileggi

April 2003

ISPD '03: Proceedings of the 2003 international symposium on Physical design

Bibliometrics:  Downloads (6 Weeks): 4,  Downloads (12 Months): 38,  Citation Count: 15

Floorplanning of pipelined array modules using sequence pairs

Matthew Moe, Herman Schmit

April 2003

ISPD '03: Proceedings of the 2003 international symposium on Physical design

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 12,  Citation Count: 1

Heterogeneous Programmable Logic Block Architectures

A. Koorapaty, V. Chandra, K. Y. Tong, C. Patel, L. Pileggi, H. Schmit

March 2003

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1 , Volume 1

Bibliometrics:  Downloads (6 Weeks): 1,  Downloads (12 Months): 21,  Citation Count: 6

Panel: Attack of the killer gate arrays

Michael Butts, Jonathan Rose, Steve Trimberger, Herman Schmit

February 2003

FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 4,  Citation Count: 0

2002

Queue Machines: Hardware Compilation in Hardware

Herman Schmit, Benjamin Levine, Benjamin Ylvisaker

September 2002

FCCM '02: Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 5

Morphable Multipliers

Silviu M. S. A. Chiricescu, Michael A. Schuette, Robin Glinton, Herman Schmit

September 2002

FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 3 

Memory optimization in single chip network switch fabrics

David Whelihan, Herman Schmit

June 2002

DAC '02: Proceedings of the 39th annual Design Automation Conference

Bibliometrics:  Downloads (6 Weeks): 2,  Downloads (12 Months): 20,  Citation Count: 7

FPGA switch block layout and evaluation

Herman Schmit, Vikas Chandra

February 2002

FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

Bibliometrics:  Downloads (6 Weeks): 5,  Downloads (12 Months): 59,  Citation Count: 6

2001

SoC Design Skills: Collaboration Builds a Stronger SoC Design Team

Pradeep Khosla, Herman Schmit, Mary Jane Irwin, N. Vijaykrishnan, Tom Cain, Steve Levitan, Dave Landis

June 2001

MSE '01: Proceedings of the 2001 International Conference on Microelectronic Systems Education (MSE'01)

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 0

2000

PipeRench implementation of the instruction path coprocessor

Yuan Chou, Pazhani Pillai, Herman Schmit, John Paul Shen

December 2000

MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Bibliometrics:  Downloads (6 Weeks): 6,  Downloads (12 Months): 38,  Citation Count: 7

Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware

Benjamin Levine, R. Reed Taylor, Herman Schmit

April 2000

FCCM '00: Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 2

PipeRench: A Reconfigurable Architecture and Compiler

Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matt Moe, R. Reed Taylor

April 2000

Computer , Volume 33 Issue 4

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 62

Pipeline Reconfigurable FPGAs

Herman H. Schmit, Srihari Cadambi, Matthew Moe, Seth C. Goldstein

March 2000

Journal of VLSI Signal Processing Systems , Volume 24 Issue 2/3

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 2

Scalable interconnect and power distribution for island-style FPGAs (poster abstract)

Herman Schmit, David Whelihan, Peter Kamarchik, Frank Gennari

February 2000

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 0 

1999

Mixed-swing quadrail for low power dual-rail domino logic

Bharath Ramasubramanian, Herman Schmit, L. Richard Carley

August 1999

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

Bibliometrics:  Downloads (6 Weeks): 4,  Downloads (12 Months): 19,  Citation Count: 3 

Vertical benchmarks for CAD

Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass

June 1999

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Bibliometrics:  Downloads (6 Weeks): 3,  Downloads (12 Months): 18,  Citation Count: 0

PipeRench: a co/processor for streaming multimedia acceleration

Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, Ronald Laufer

May 1999

ISCA '99: Proceedings of the 26th annual international symposium on Computer architecture

Bibliometrics:  Downloads (6 Weeks): 12,  Downloads (12 Months): 47,  Citation Count: 61

PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing

Ronald Laufer, R. Reed Taylor, Herman Schmit

April 1999

FCCM '99: Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 6

Extra-dimensional island-style FPGAs (abstract only)

Herman Schmit

February 1999

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 6,  Citation Count: 1 

1998

Characterization and Parameterization of a Pipeline Reconfigurable FPGA

Matthew Moe, Herman Schmit, Seth Copen Goldstein

April 1998

FCCM '98: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 0

Managing pipeline-reconfigurable FPGAs

Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas

March 1998

FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Bibliometrics:  Downloads (6 Weeks): 1,  Downloads (12 Months): 27,  Citation Count: 9

1997

Incremental reconfiguration for pipelined applications

H. Schmit

April 1997

FCCM '97: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 15

Synthesis of application-specific memory designs

Herman Schmit, Donald E. Thomas

March 1997

IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Volume 5 Issue 1

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 24

Is reconfigurable computing commercially viable (panel)?

Herman Schmit

February 1997

FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 4,  Citation Count: 0 

1996

Synthesis of application-specific memory structures

Herman Henry Schmit

October 1996

Synthesis of application-specific memory structures

Publisher: Carnegie Mellon UniversitY

1995

Address generation for memories containing multiple arrays

Herman Schmit, Donald E. Thomas

December 1995

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 8,  Citation Count: 6

Array mapping in behavioral synthesis

Herman Schmit, Donald E. Thomas

September 1995

ISSS '95: Proceedings of the 8th international symposium on System synthesis

Bibliometrics:  Downloads (6 Weeks): 0,  Downloads (12 Months): 12,  Citation Count: 6

Hidden Markov modeling and fuzzy controllers in FPGAs

H. Schmit, D. Thomas

April 1995

FCCM '95: Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 4

1993

A Model and Methodology for Hardware-Software Codesign

Donald E. Thomas, Jay K. Adams, Herman Schmit

July 1993

IEEE Design & Test , Volume 10 Issue 3

Bibliometrics:  Downloads (6 Weeks): n/a,  Downloads (12 Months): n/a,  Citation Count: 65

Issued US Patents

9,813,061 Circuitry for implementing multi-mode redundancy and arithmetic functions

9,806,696 Systems and methods for a low hold-time sequential input stage

9,768,783 Methods for operating configurable storage and processing blocks at double and single data rates

9,755,647 Techniques for handling high voltage circuitry in an integrated circuit

9,740,808 Method and apparatus for implementing a system-level design tool for design planning and architecture exploration

9,692,418 Pipelined interconnect circuitry with double data rate interconnections

9,606,573 Configurable clock grid structures

9,582,349 Methods and apparatus for detecting memory bit corruption on an integrated circuit

9,553,762 Network-on-chip with fixed and configurable functions

9,507,900 Method and apparatus for decomposing functions in a configurable IC

9,507,883 Method and apparatus for implementing a system-level design tool for design planning and architecture exploration

9,490,814 Configurable IC having a routing fabric with storage elements

9,489,175 Configurable IC's with large carry chains

9,479,456 Programmable logic device with integrated network-on-chip

9,450,609 Methods and apparatus for embedding an error correction code in memory cells

9,385,725 Runtime loading of configuration data in a configurable IC

9,385,724 Methods for operating configurable storage and processing blocks at double and single data rates

9,369,363 Apparatus and methods for determining latency of a network port

9,362,913 Circuitry for implementing multi-mode redundancy and arithmetic functions

9,300,421 Methods to achieve accurate time stamp in IEEE 1588 for system with FEC encoder

9,197,531 Methods and apparatus of time stamping for multi-lane protocols

9,165,931 Apparatus for field-programmable gate array with configurable architecture and associated methods

9,118,566 Methods and apparatus of time stamping for multi-lane protocols

9,083,478 Apparatus and methods for determining latency of a network port

9,041,430 Operational time extension

9,018,978 Runtime loading of configuration data in a configurable IC

9,018,977 User registers implemented with routing circuits in a configurable IC

8,810,277 Non-sequentially configurable IC

8,797,062 Configurable IC's with large carry chains

8,760,194 Runtime loading of configuration data in a configurable IC

8,726,213 Method and apparatus for decomposing functions in a configurable IC

8,723,549 Configurable IC having a routing fabric with storage elements

8,664,974 Operational time extension

8,638,119 Configurable circuits, IC's, and systems

8,436,700 MEMS-based switching

8,434,045 System and method of providing a memory hierarchy

8,433,891 Accessing multiple user states concurrently in a configurable IC

8,339,844 Programmable vias for structured ASICs

8,305,110 Non-sequentially configurable IC

8,248,102 Configurable IC'S with large carry chains

8,230,182 System and method for providing more logical memory ports than physical memory ports

8,193,830 Configurable circuits, IC's, and systems

8,183,882 Reconfigurable IC that has sections running at different reconfiguration rates

8,115,510 Configuration network for an IC

8,093,922 Configurable IC having a routing fabric with storage elements

8,067,960 Runtime loading of configuration data in a configurable IC

7,962,705 System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture

7,948,266 Non-sequentially configurable IC

7,932,742 Configurable IC with interconnect circuits that have select lines driven by user signals

7,930,666 System and method of providing a memory hierarchy

7,898,291 Operational time extension

7,872,496 Method of mapping a user design defined for a user design cycle to an IC

7,839,166 Configurable IC with logic resources with offset connections

7,804,730 Method and apparatus for accessing contents of memory cells

7,797,497 System and method for providing more logical memory ports than physical memory ports7,788,478 Accessing multiple user states concurrently in a configurable IC7,765,249 Use of hybrid interconnect/logic circuits for multiplication

7,759,971 Single via structured IC device

7,743,085 Configurable IC with large carry chains

7,711,964 Method of securing programmable logic configuration data

7,696,780 Runtime loading of configuration data in a configurable IC

7,694,083 System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture

7,667,486 Non-sequentially configurable IC

7,656,188 Reconfigurable IC that has sections running at different reconfiguration rates

7,652,499 Embedding memory within tile arrangement of an integrated circuit

7,626,419 Via programmable gate array with offset bit lines

7,622,951 Via programmable gate array with offset direct connections

7,616,027 Configurable circuits, IC's and systems

7,609,085 Configurable integrated circuit with a 4-to-1 multiplexer

7,595,655 Retrieving data from a configurable IC

7,587,69 8Operational time extension

7,587,697 System and method of mapping memory blocks in a configurable integrated circuit

7,576,564 Configurable IC with routing circuits with offset connections

7,573,296 Configurable IC with configurable routing resources that have asymmetric input and/or outputs

7,564,261 Embedding memory between tile arrangement of a configurable IC

7,564,260 VPA interconnect circuit

7,548,085 Random access of user design states in a configurable IC

7,545,167 Configurable IC with interconnect circuits that also perform storage operations

7,532,032 Configurable circuits, IC's, and systems

7,530,033 Method and apparatus for decomposing functions in a configurable IC

7,528,627 Method and apparatus for performing shifting in an integrated circuit

7,525,344 Configurable IC having a routing fabric with storage elements

7,525,342 Reconfigurable IC that has sections running at different looperness

7,521,958 Hybrid configurable circuit for a configurable IC

7,518,402 Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs

7,518,400 Barrel shifter implemented on a configurable integrated circuit

7,514,957 Configurable IC having a routing fabric with storage elements

7,512,850 Checkpointing user design states in a configurable IC

7,504,858 Configurable integrated circuit with parallel non-neighboring offset connections

7,492,186 Runtime loading of configuration data in a configurable IC

7,489,162 Users registers in a reconfigurable IC

7,449,915 VPA logic circuits

7,443,196 Configuration network for a configurable IC

7,439,766 Configurable logic circuits with commutative properties

7,425,841 Configurable circuits, IC's, and systems

7,420,389 Clock distribution in a configurable IC

7,408,382 Configurable circuits, IC's, and systems

7,342,415 Configurable IC with interconnect circuits that also perform storage operations

7,317,331 Reconfigurable IC that has sections running at different reconfiguration rates

7,310,003 Configurable IC with interconnect circuits that have select lines driven by user signals

7,307,449 Sub-cycle configurable hybrid logic/interconnect circuit

7,301,368 Embedding memory within tile arrangement of a configurable IC

7,298,169 Hybrid logic/interconnect circuit in a configurable IC

7,295,037 Configurable IC with routing circuits with offset connections

7,282,950 Configurable IC's with logic resources with offset connections

7,276,933 Reconfigurable IC that has sections running at different looperness

7,263,602 Programmable pipeline fabric utilizing partially global configuration buses

7,262,633 Via programmable gate array with offset bit lines

7,259,587 Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs

7,242,216 Embedding memory between tile arrangement of a configurable IC

7,236,009 Operational time extension

7,230,869 Method and apparatus for accessing contents of memory cells

7,224,182 Hybrid configurable circuit for a configurable IC

7,224,181 Clock distribution in a configurable IC

7,197,647 Method of securing programmable logic configuration data

7,193,440 Configurable circuits, IC's, and systems

7,193,432 VPA logic circuits

7,167,025 Non-sequentially configurable IC

7,157,933 Configurable circuits, IC's, and systems

7,131,017 Programmable pipeline fabric having mechanism to terminate signal propagation

7,126,381 VPA interconnect circuit

7,126,373 Configurable logic circuits with commutative properties

7,109,752 Configurable circuits, IC's, and systems

6,633,182 Programmable gate array based on configurable metal interconnect vias

6,366,061 Multiple power supply circuit architecture