Shi Chen

Summary

I describe myself as a very dynamic individual with a strong team attitude who can simultaneously handle a variety of tasks under minimal supervision while holding a blend of technical and analytical expertise. I feel confident that my abilities will help me follow through the activities involved in this position.

At Memorial University, I took part in a vector computing project for a special Earth structure simulation model. I implemented floating point arithmetic units, such as adder, multiplier, and multiply-add-fused, on Altera and Xilinx FPGA platform. Thus, I studied computer arithmetic, computer architecture, and digital design. Eventually, I became comfortable with FPGA design environment and optimization method. The VHDL models of floating point arithmetic units were packed into the vector computing system. Also, I complied with FPGA design flow and documented all FPGA techniques applied on the embedded system. In order to choose the most suitable platform, I worked on an evaluation report on several products that offer the compatibility and the functionality required. A paper entitled "Implementation of Vector Floating-point processing unit on FPGAs for high performance computing" was published in CCECE 2008 and was awarded as best student paper.

Additionally, during my experience in Beijing Wisewell Avionics Corporation, I was in charge of designing drivers and applications for embedded system, including VxWorks 5.5/ Tornado 2.2. Using C language, I worked different BSP driver for both x86 and PPC platform, and various applications dealing with different avionics requirements.

Objective

Embedded Software Engineer or Hardware Designer (FPGA)

Work History

Work History

Embedded Software Engineer

Wisewell Avionics Corporation

I Implemented BSP and Application module of the Graphics Display System for fixed wing airplane using VxWorks/Tornado on both x86 and PPC platform. I was promoted as Project Manager 6 months after hiring date because of excellent work record. After one year, my team completed Engine Indicating and Crew Alerting System (EICAS) for helicopter and attended Honeywell Six-Sigma training.

May 2004 - Aug 2005

Embedded Software Engineer

NetChina Communication Corp.

I was a software engineer in a network communication corporation, NetChina Communication Corporation. We completed the UML model of a distributed firewall system using Rational Rose and implemented using C/C++, which connected the traditional boundary firewall based on FreeBSD and desktop firewall software. I mainly completed the control center part and common communication module, which use UDP mode to send the encrypt rule package. The communication module is designed for three OS platform: FreeBSD(boundary firewall), Win32(desktop firewall), and Linux(control center).

Education

Education
Sep 2005 - May 2008

Master of Engineering

http://www.mun.ca

At Memorial University, I took part in a vector computing project for a special Earth structure simulation model. I implemented floating point arithmetic units, such as adder, multiplier, and multiply-add-fused, on Altera and Xilinx FPGA platform. Thus, I studied computer arithmetic, computer architecture, and digital design. Eventually, I became comfortable with FPGA design environment and optimization method. The VHDL models of floating point arithmetic units were packed into the vector computing system. Also, I complied with FPGA design flow and documented all FPGA techniques applied on the embedded system. In order to choose the most suitable platform, I worked on an evaluation report on several products that offer the compatibility and the functionality required. A paper entitled "Implementation of Vector Floating-point processing unit on FPGAs for high performance computing" was published in CCECE 2008 and was awarded as best student paper.

Skills

Skills

C/C++

Excellent in C/C++, familiar with OOP familiar with low level programming Familiar with VxWorks/Tornado and embedded Linux development environment

VHDL

Excellent in RTL Coding using VHDL/Verilog Familiar with FPGA development on Xilinx Virtex II Pro (ISP & EDK 8.2i) and Altera Cyclone II (Quartus II).