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Chung Hsinn Yang

Sr. Process Engineer at TEL FSI


An expert in semiconductor wet clean process. Over 12 years experience in semiconductor industry and most time focus on wet clean/etching processes. Flexible for any positions, locations and roles.

Worked in fab one year to plot run new production and managed whole fab monitor and dummy wafer recycle system. Well knew of fab working environment.

Worked in equipment vendor field application engineer for seven years to demonstrate new tools and processes at customer site. Made all demonstrations successful and built up good relationship with customers for future new processes development. Well knew of equipment vendor working culture and how to service customer.  

Worked in equipment vendor lab to develop new processes to meet customer requirement. Well knew how a lab working and operation.

Work experience

Feb 2013Mar 2016

Sr. Process Engineer

TEL FSI, Chsaka, MN, U.S.A

Employed as a senior process engineer in lab to develop new BEOL wet clean process, and FEOL etch process.

  • Responsible for BEOL (Back End of Line) wet process maintained and developed new application in the process lab. Include HF (Hydrofluoric acid) - Citric clean process, HF etching process, TMAH (tetramethylazanium hydroxide) etch process, dilute NH4OH (Ammonia) etch process, DSP (dilute sulfuric Hydrogen peroxide mixing) clean process…etc
  • Transferred new processes from lab to filed including provide training classes on site.
  • Co-worked with R&D team for new remote chemical supply system designing, tuning and testing.
  • Traveling for field process support.
  • FEOL (Front End of Line) wet process supported. Especially HF etching process set up and tuning for FEOL.
  • Field wafer process demonstration execution.
  • Lab single wafer clean system processes maintained.
Jul 2005Feb 2013

Sr. Application Engineer

FSI International Asia Ltd. Hsinchu, Taiwan

Employed as a field application engineer in charge of service major Asian customers. Long term on site supported different customers and got successful result. 

  • Applied new processes for our new single wafer clean system at customer site.
  • Developed new FEOL (Front End of Line) wet clean processes to compete with other competitors in the industry.
  • Co-worked with customer’s R&D process team to develop new patent wet processes for new technology node.
  • Leaded research with process engineering team with customer to improve process performance and reduce process cost. Write process recipes for FSI clean system.
  • DOE for checking process window and tuning process target.
  • Troubleshooted process issues and helped to set up experiments for equipment engineer to check equipment component conditions.
  • Provided semiconductor wet process classes and FSI clean system operation training and demonstrations to customer.
  • Supported FSI lab remote demonstration work. Scheduled demonstration work and coordinated customer’s expectation and FSI lab process capability. Tracked demonstration progress and check result with customer.
  • Systematic market intelligence collected. Collected customer current process baseline information and next generation development pattern.
  • Co-worked with customer to publish semiconductor wet clean process technological paper.
Feb 2004Jun 2005

Process Engineer

Inotera Memories, Inc. Taoyuan, Taiwan

Employed as a process engineer of diffusion department. Major in charge of FEOL wet process and atmosphere furnace CVD process. I experienced whole new fab hook-up, that included

  • New process equipment moved-in and qualified.
  • New FEOL wet processes developed 
  • Deep trench 110nm and 90nm DRAM process plot run.
  • Whole fab monitor wafers and dummy wafers recycling system control.


Sep 2000Jul 2002


National Central University, Taoyuan, Taiwan

Atmospheric Physics

Sep 1996Jun 2000


National Central University, Taoyuan, Taiwan

Atmospheric Sciences


  • English - Professional working proficiency
  • Chinese - Native language 


Semiconductor Wet Clean/Etch Process  

Over 12 years 300mm wet clean/etch processes over FEOL, MEOL, BEOL in both wet bench and single wafer tool.

Semiconductor CVD Proess LP-furnace , AP-furnace.

Familiar with AP and LP furnace process 

Windows, Office, UNIX, Fortran

Regular using Windows OS and office program, also familiar with UNIX system and Fortran.