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Work experience

2015Present

Senior Hardware Engineer

Frontline Test Equipment / Teledyne Lecroy

Developed a wideband SDR packet sniffer for Bluetooth (BR/EDR and BLE). Released all Bluetooth 5.0 features before spec adoption.

  • Detailed knowledge of the Bluetooth core specification (4.2, 5.0, and 5.1 drafts)
  • Xilinx Zynq SoC and associated tool chains (Vivado, PetaLinux and legacy ISE)
  • DSP algorithm development (polyphase channelizers, demodulator, and synchronization)
  • Modeling in MATLAB and implementation in Verilog/VHDL 
  • 2.4 GHz RF front end design
  • Product development and manufacturing
2014Present

Owner / Principal Consultant

CGSDR

Consulting and contract work related to software defined radio and communication system design.

  • Communication system modeling and simulation
  • SDR hardware experience: USRP, LimeSDR, PicoZed SDR, RTL-SDR
  • FPGA hardware experience: Zedboard, MicroZed, Trenz TE0720
  • RF front end experience: AD9361, AD9364, AD9371, LMS6002, LMS7002
  • GnuRadio, Python, MATLAB, Simulink HDL Coder
  • KiCad, Eagle, FreeCad
  • Turbo-codes
20132015

Communication Systems Engineer

IMSAR

Built a long range RFID asset localization system based on TDoA and AoA techniques. Reduced cost and improved position accuracy over previous generation system.

  • FPGA based SDR receiver with Xilinx Zynq SoC (Vivado)
  • Algorithm development and simulation (Python NumPy, MATLAB)
  • Product development and manufacturing
  • 915 MHz RF front end design and prototyping
  • Precision synchronization algorithms
  • Solar energy harvesting
  • FCC certification
20102013

Research Engineer

FreeLinc

Designed and implemented an SDR platform for near-field magnetic induction IP development, testing, and demonstration. Led the project and a team of 5 engineers from concept to release.

  • Custom FPGA-based SDR transceiver with Altera Cyclone III (Quartus, DSP Builder)
  • Ground-up design of PHY and MAC layers
  • RFID and NFC protocols
  • Hardware prototyping

Education