Celia Clause

Director of Engineering

Summary

Experience leading a team of engineers in designing and validating products in the video, audio and telecommunications industry.  Strong track record leading engineering team members in their growth and development. Skilled in spanning multiple programs and interfacing with a number of engineering teams. Creatively work with the team to implement best known methods for product design and validation and continuously improve. Strong interpersonal skills in communication, delegation and follow up.

Work History

Work History
2007 - 2015

Senior Staff Engineer

Avnera Corporation, Beaverton OR
  • Responsible for overseeing the validation of 8 system-on-a-chip designs, including the real time FPGA prototype hardware and software for the digital subsystem.
  • Designed and implemented Python, C and Java interfaces to the FPGA prototype to allow firmware prototyping and system integration and validation.
  • Worked directly with the firmware team to plan all of the required firmware for hardware validation and used their feedback to improve integrated circuit architecture.
2005 - 2007

Director IC Engineering

Enuclia Corporation, Beaverton OR
  • Supervised a team of twelve engineers responsible for the design and verification of flat panel display integrated circuits.
  • Worked with the business team to prioritize bug fixes and feature requests.
  • Provided technical leadership in the development of an object-oriented environment for prototyping the entire product including DSP algorithms to validate the system design.
  • Handled recruitment, training and performance management of team members.
2003 - 2005

Staff Engineer

Intel Corporation, Hillsboro OR
  • Lead engineer for the verification multiple generations of 802.11 and Bluetooth integrated circuits using the Specman Elite aspect oriented language.
1997 - 2003

Senior Design Engineer

Qualis Corporation, Lake Oswego OR
  • Project Lead and primary contributor in System Verilog, Specman and VERA based verification components and instructor for verification classes in System Verilog, Specman Elite, and VHDL in the USA, UK, Germany, France.
1995 - 1997

ASIC Design Engineer

RadiSys Corporation Beaverton OR
  • Responsible for design, integration and test of subsystems into a 486 companion chip.
1992 - 1995

ASIC Design Engineer

Exabyte Corporation, Boulder CO
  • ┬áDesigned, implemented and tested various subsystems including a DMA Interface, DRAM Controller, high speed search circuitry, cartridge and tape path control, and erase clock.

Education

Education
1991

Bachelors in Electrical Engineering

University of Colorado Boulder CO

Skills

  • Java
  • C/C++
  • Python
  • JSON
  • HTML
  • System Verilog
  • VHDL
  • System C
  • Perl
  • Knowledge of Agile methodologies