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Profile Summary

  • Qualified for Intern program at CVC Pvt. Ltd. in ASIC Design and Verification.
  • Selected in Cadence Design Challenge 2015 for an innovative abstract / project idea in  Analog IC design.
  • Established an web based electronics training,consulting forum(NOVUDUX).
  • Holding the 2nd rank as per the university toppers list for the batch 2010-14.
  • Successfully conducted many workshops on recent trends in the field of electronics.
  • Qualified GATE-2014 (ECE).


Jun 2014Present


CDAC Mohali

VLSI Design                                                          Percentage:  80%

Jul 2010May 2014


Sambalpur University

Electronics and Communication Engineering   Percentage,CGPA: 89.2%, 9.42

Projects & Developments

  • Developed a branch predictor IP for pipelines FPGA prototyping processors in verilog.
  • Successfully customized and implemented a Linux RTOS for ZED Board to design a Wireless Sensor Network.
  • Designed and implemented  audio and video processing through HDMI on Zynq Processor (ZC702 SOC) .


May 2013Jul 2013

SOC IP Development

Central University of Hyderabad

"IP Development and Embedded Design in SOC Platform"


May 2012Jun 2012

Image Processing

Central University Of Hyderabad

"Implementing image processing algorithms for machine vision" 


LAB View

National Instruments

Expertise labview tool environment


PCB Designing And Fabrication

Pupils Paradise

Fabricated home made PCBs 

Personal Information

  • Languages Known: English, Hindi, Oriya
  • Marital Status: Single
  • Gender: Male
  • Nationality: Indian
  • DOB: 20/07/1992
  • Hobbies: surfing and implementing new technologies, playing cricket.


I hereby declare that all the information furnished in this resume is complete and correct to the best of my knowledge and belief.

Barada Prasanna Biswal

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