Profile Summary



Jun 2014 - Present


CDAC Mohali

VLSI Design                                                          Percentage:  80%

Jul 2010 - May 2014


Sambalpur University

Electronics and Communication Engineering   Percentage,CGPA: 89.2%, 9.42

Projects & Developments

  • Developed a branch predictor IP for pipelines FPGA prototyping processors in verilog.
  • Successfully customized and implemented a Linux RTOS for ZED Board to design a Wireless Sensor Network.
  • Designed and implemented  audio and video processing through HDMI on Zynq Processor (ZC702 SOC) .


May 2013 - Jul 2013

SOC IP Development

Central University of Hyderabad

"IP Development and Embedded Design in SOC Platform"


May 2012 - Jun 2012

Image Processing 

Central University Of Hyderabad

"Implementing image processing algorithms for machine vision" 

2012 - 2012

LAB View

National Instruments

Expertise labview tool environment

2011 - 2011

PCB Designing And Fabrication

Pupils Paradise

Fabricated home made PCBs 

Personal Information

  • Languages Known: English, Hindi, Oriya
  • Marital Status: Single
  • Gender: Male
  • Nationality: Indian
  • DOB: 20/07/1992
  • Hobbies: surfing and implementing new technologies, playing cricket.


I hereby declare that all the information furnished in this resume is complete and correct to the best of my knowledge and belief.

Barada Prasanna Biswal