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Electronic Design Automation R&D engineer with Intel's Xeon/Core business.

Work experience

Sep 2009Present

EDA R&D Engineer


Work with multiple teams spread across 3 continents to deliver tool automation for design and validation of next generation Xeon and Core i3/5/7 products. 

Aug 2008May 2009

Component Design Intern


Worked on 3d/2d graphics debug with the chipset validation team enabling emulation of next generation chipsets and discrete graphics solutions. Assisted in creating emulation friendly models based on actual RTL and enabled low-level debug features for pre/post-silicon debug teams. Also have peripheral debug experience through supporting teams on next generation peripheral debug and bug fix. Involved training on emulation architectures, place and route of logic on FPGAs and modeling emulation-friendly RTL. Received recognition for supporting virtualization teams on low-level debug.

Aug 2007Aug 2008

Graduate Assistant

Designed and implemented an information system spanning all 3 campuses to enable budget allocation for various projects current or planned upto 2020.

Keyword's: SQL Server, MS Access, ASP, HTML, XML

Jan 2007Dec 2007

Teaching Assistant/Instructor

  • Designed and instructed an undergraduate course to develop a solid understanding in Digital Design fundamentals.
Aug 2006Dec 2006

Research Assistant

Developed a Bayesian model to estimate output fault behavior due to spatio-temporal faults induced in high-k dielectrics.


  • Analysis and characterization of temporal errors induced in standard benchmark circuits due to device aging and process variations. The fault analysis and characterization was done using HUGIN API on Visual C++ and validated in HSPICE using standard 45nm Predictive Technology models (PTM). Waveform sampling and fitting was done using MATLAB. A similar model was developed for Single Electron Transistors (SET) and simulated using SIMON.
  • Developed an elegant model for the spatial errors induced in standard benchmark circuits due to temporal faults induced in neighboring circuits. Analyzed and proposed various redundancy methods and optimal input vector patterns to mask errors at the Gate-level. The Bayesian network model was simulated using HUGIN API on Visual C++ and results validated using HSPICE. The results were also applied to Single Electron Transistor (SET) circuits and simulated using SIMON and MATLAB.
  • Created a High-k dielectric low-Weibull slope aware model for 32nm CMOS technology with specific emphasis on the fault characterization due to soft errors. The soft error rate was predicted using HUGIN API on Visual C++ and validated in HSPICE using High-k 32nm Predictive Technology Models. MATLAB and Origin Pro were used to fit and sample curves.
  • Modeled the input space for standard benchmark circuits
  • Investigated the effect of cosmic ray bombardment at various altitudes on a variety of High-k materials. Samples were prepared at the Nanomaterials and Nanomanufacturing Research Center (NNRC) and actual testing was performed at various altitudes in Tampa, Florida.
  • Developed code to construct a Bayesian Network emulating the behavior of standard ISCAS ’85 benchmark circuits. Belief propagation can be performed using standard simulators such as HUGIN or GeNie.




  • 16-bit Carry Look-Ahead adder using Xilinx ISE and Altera Maxplus II in VHDL.
  • 4-bit Ripple Carry Adder using Cadence Virtuoso and HSPICE.
  • 4-bit 10 kbps Successive Approximation Analog to Digital converter using ADS and PSPICE.
  • Image processing tool for Colbert Green Screen Challenge using Tree & Forest ADTs.
Jul 2002Jul 2006


Anna University

Senior Design Project

Designed and implemented an automated database system based on Radio Frequency Identification (RFID) for the college library. Anti-Collision algorithms were built into standard readers and tested using a sample population of 500 people. Installed displays to indicate the location of related books or digital titles. Eliminated long lines and administrative difficulties as a result.


Coding - C
Designed image processing tool for Colbert Green Screen Challenge using ADT's such as Tree, Forest and Linked Lists. Created tool to process ISCAS Benchmarks and port them as 2-input Bayesian networks. Created code to use HUGIN API to propagate faults and poll output nodes for resultant behavior. Randomized and automated vector generation for HSPICE simulations based on finite automata.  
Completed training on various nuances of emulation using Mentor Graphics Veloce/Vstation VPRO including setting up of targets and test cards for USB 3.0 and SATA. Assisted in waveform capture for low level firmaware and graphics 2D/3D debug.
Automated several pre-silicon validation processes at Intel.
Reviewed/Modified RTL for several important leadership products at Intel.