Anjali Tailor

  • Surat GJ

DFT Engineer


  • Recently joined graphene semiconductor, Bangalore from June, 2015
  • 2 years of experience as a VLSI engineer at eInfochips, Ahmedabad.
  • 1.6 months of experience as a DFT(Design For Testability) VLSI engineer at eInfochips, Ahmedabad.
  • Professional training of 6 months in Physical Design and DFT domain from eInfochips (eiTRA), Ahmedabad.
  • Experience in analyzing customer’s requirements and providing solutions. Possess proficiency in grasping technical concepts quickly and utilizing same in a productive manners.


2009 - 2013

Bachelor of Engineering in Electronics Engineering

Birla vishwakarma Mahavidyalaya, GTU

July 2009 - May 2013

CGPA - 8.12



ATPG : Mentor

ATPG in various modes of SSA and TR. DRC violation fixing.

ATPG : Tetramax

ATPG in various modes of SSA and TR. DRC violation fixing, Test Coverage Analysis.

Pattern Validation

Pattern simulation and validation (With and without timing)

Memory BIST

Tessent MBIST : Block level Memory BIST insertion and validation

Logic BIST

Pattern generation and validation : LBIST

Synopsys : SHS and SMS

Star Builder, Star Integrator and Yield Accelerator tools by synopsys for memory and IP validation. Stat Hierarchical System and Star Memory System(5.0)

Scan Insertion

Scan insertion : Incentia TestCraft

IEEE standards

IEEE 1149. 1 and IEEE P1500

Advanced Fault Models

Path Delay and Small Delay Defect testing

IJTAG standard


Test Compression

Test compression architecture and X-masking techniques for DFTMAX and Tessent TestKompress

Professional Experiences

Work History
Mar 2015 - Dec 2015

Project #1

Technology : 40 nm

Roles and Responsibilities:
1. Block level Memory BIST Architecture Insertion using Tessent MBIST and performing Logic Equivalence Checking

  •  Memory grouping according to the customer specific requirements.
  • MBIST insertion at block level and IEEE1500 Standard implementation for Memory tesing. Including EFUSE insertion and BISR architecture for repairable memories.

2. Block Level Scan Insertion, Compression Architecture Insertion using Incentia Test Craft and TestKompress Mentor Graphics.

  • DRC violation analysis/ debugging and ECO using customer utility if violation exists.
  •  Scan Architecture implementation and Compression architecture implementation according to customer specific requirements.
  • Logical Equivalence checking to confirm if functionality is changed or not.

3. Block Level Pattern generation using Fast Scan Mentor Graphics.
4. Extracted Timing Model generation using primetime


  • Understanding flow related to Incentia Test Craft, TestKompress and Fast Scan by Mentor Graphics.
  • Faced DRC violation in Scan Insertion/ ATPG/ LEC/ ETM model generation.

Nov 2014 - Feb 2015

Project #2

Technology : 28 nm

Roles and Responsibilities:
1. Memory and IP testing

  • Worked on functional IP testing using Synopsys SHS (STAR Hierarchical System) flow and memory testing using Synopsys SMS (STAR Memory System) flow.
  • Use of STAR Integrator tool to generate wrapper RTL for IPs or Memories and server RTL for top-level SoC.
  • Use of STAR Builder tool to insert and integrate the wrapper RTL at subchip or SoC level and the server RTL on SoC level.
  • Use of STAR Verifier tool to generate top level testbencd and pattern generation.

2. ATPG pattern generation and validation

  • Worked on Pattern generation for Single Stuck At (Compressed mode) using Encounter Test by Cadence.
  • Pattern validation (with and without timing) using NC Verilog simulator.


  • Understanding flow related to Encounter Test pattern generation.
  • Simulation hanging issue.
  • Understanding of new Synopsys SHS and SMS flow for IP and memory testing.
Dec 2013 - Oct 2014

Project #3

Technology : 28 nm

Roles and Responsibilities:
1. MBIST Validation

  • P1687 implemented SoC for MBIST architecture.
  • SoC level Memory BIST Pattern generation and validation.
  • Pattern generation and validation for RAM EFUSE Interface(REI) architecture testing.
  • Pattern generation and validation for burn in environment testing.
  • Memory size of more than 800MB.

2. LBIST Validation

  • Logic BIST pattern generation and validation.
  • Analysis for failure debugging.


  • Used Tetramax Synopsys for Pattern generation.
  • Single Stuck-at and Transition faults test vector generation in compressed and uncompressed mode.
  • Test coverage analysis, improvement and achievement.
  • Test Vector simulation and Validation.

4. IO Test

  • Several tests are performed to detect the defect in the I/O pads like bsdl_dut_in, bsdl_dut_out, leakage test, loop test, idcode test, acextest

5. Miscellaneous Tests

  • PLL test, PMRO test, Thermal Sensor test


  • Memory BIST pattern validation failure mismatches analysis.
  • REI failure debugging.
  • DRC violation, coverage improvement techniques.
  • Understanding customer specific flow, having IJTAG implementation.


eITRA(eInfochips Training and Reserch Academy                                                                            July 2013 - November 2013
Ahmedabad, Gujarat, India

  • Good Fundamental Knowledge on every stage of Back end Design
  • Physical design flow in Synopsys IC Compiler: Floor planning, Power Planning, Placement, Routing, CTS and basic knowledge of physical verification
  • Static Timing Analysis techniques, Setup time requirements, Hold time requirements, Timing Design Constraints, Design reports, Clock timing issues, Timing exception, Pre-layout timing analysis
  • Synthesis design flow in Synopsys DC Compiler, optimization techniques.
  • Good fundamental knowledge on Signal Integrity and crosstalk.
  • Sound knowledge on advance topic like, OCV and MCMM.

Project Description:

  • Instance count of 70K, 342MHz frequency.
  • Involved in Floorplanning, Power Planning, CTS, Routing.
  • Used IC Compiler by Synopsys.


  • Understanding Physical Design flow on IC Compiler.
  • Congestion issue resolution.