eITRA(eInfochips Training and Reserch Academy July 2013 - November 2013
Ahmedabad, Gujarat, India
- Good Fundamental Knowledge on every stage of Back end Design
- Physical design flow in Synopsys IC Compiler: Floor planning, Power Planning, Placement, Routing, CTS and basic knowledge of physical verification
- Static Timing Analysis techniques, Setup time requirements, Hold time requirements, Timing Design Constraints, Design reports, Clock timing issues, Timing exception, Pre-layout timing analysis
- Synthesis design flow in Synopsys DC Compiler, optimization techniques.
- Good fundamental knowledge on Signal Integrity and crosstalk.
- Sound knowledge on advance topic like, OCV and MCMM.
- Instance count of 70K, 342MHz frequency.
- Involved in Floorplanning, Power Planning, CTS, Routing.
- Used IC Compiler by Synopsys.
- Understanding Physical Design flow on IC Compiler.
- Congestion issue resolution.