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Velankani Electronics Private Limited                                                                                         June 2016 to Present
Currently working on Solid State drive (SSD) project at VEPL



Master of Science by Research

International Institute of information Technology, Bangalore

Electronic System Design (GPA- 3.1/4)
Supervisor : Prof. Subir K. Roy
Summary: This work attempts to formally verifying AMS designs and to incorporate simulation traces in the formal model of AMS designs in order to develop and verify exact model of the AMS system.


Bachelor of Technology

Institute of Technology, Guru Ghasidas Vishwavidyalaya, Bilaspur (CG)

Electronics and Communications Engineering (GPA- 8.91/10)


Intermediate (10+2)

Kendriya Vidyalaya IffcoPhulpur Allahabad

CBSE - (82.8%)


High School (10th)

Kendriya Vidyalaya IffcoPhulpur Allahabad

CBSE - (87%)


Programming Languages- ASSEMBLY (8085, x86), C, C++, MATLAB ;Hardware Description Languages- VHDL, VERILOG, SYSTEM VERILOG (Beginner) ;Spice Tools- CADANCE VIRTUOSO, LT SPICE, MODELSIM; Layout Design Tools- MICROWIND, ELECTRIC; Operating Systems- WINDOWS, LINUX; FPGA Design Tools- XILINX ISE; Verification Methodology- UVM(Basics)


  • Ambuj Mishra & Subir K. Roy, “Towards Formal Verification of Adaptive Cruise Controller using SpaceEx”, 2016 VLSI Systems Architecture, Technology and Applications Conference, VLSI-SATA, Bangalore.
  • Ambuj Mishra & Subir K Roy, “Formal Verification of Switched Capacitor DC to DC Power Converter Using Spice Simulation Traces”, 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati


Jan 2014Feb 2014

Design and Verification of UART


Designed UART module with baud rate of 9600, which has been modelled using Verilog HDL and have written test benches to verify using Mentor Graphics Modelsim.

Sep 2013Dec 2013

Functional Verification of I2C Master Controller


Involved in functional verification of I2C Master Byte and Bit Controller Blocks. Verified using Formal approach by specifying properties in LTL using VIS tool.

Sep 2013Dec 2013

Design of Low Power and High Gain two stage CMOS Comparator


Three models of comparators were designed to achieve high gain (>10000), high bandwidth (>1 MHz) at lowest possible power supply.

Sep 2013Nov 2013

Layout Design of 16 function ALU


It involved design of Schematic and Layout of 16 function Arithmetic and Logic Unit using Electric Tool.

Jan 2013Apr 2013

Interfacing VGA monitor with Xilinx FPGA

IT-GGV Bilaspur (CG)

This project introduces the basics of developing a simple VGA handler in VHDL. 

Jul 2012Nov 2012

Design of two stage CMOS operational amplifier using LT-Spice

IT-GGV Bilaspur (CG)

This project is related to the implementation of the theories learnt in VLSI and analog electronics in order to design an improved amplifier in terms of gain and bandwidth etc. using simulation software LTSPICE. 


  • Internship on Image Processing (“Pattern Recognition”) under Prof. Mahua Bhattacharya
    (ABV-IIITM, GWALIOR)                                                                                                       June 2011 to June 2011
  • Training on Advance Telecommunication (BSNL BILASPUR)                                        June 2012 to June 2012
  • National Workshop on Electronic System Level Design And Verification
    (Amrita Vishwa Vidyapeetham)                                                                                             14th-15th Nov. 2014
  • Attended a tutorial on UVM (Universal Verification Methodology), at VLSI Systems, Architecture, Technology and Applications,(VLSI-SATA) 2016, Bangalore
  • Attended India Electronics and Semiconductor Association (IESA) Summit 2016, Bangalore

Academic and Extra Curricular Accomplishments

  • Selected in National Standard Examination in Physics 2006 - 2007
  • Participated in Arthrobotics, a workshop on Legged Robotics conducted by Technophilia in association with Techkriti-2010- IIT KANPUR
  • College Ambassador for ITGGV in Techkriti-2012 IIT KANPUR
  • Team Leader of sponsorship team in Equilibrio-2012, annual technical festival of ITGGV Bilaspur (CG).
  • GATE-2013 qualified (ECE)